sync_up: Add meeting notes page for next week.

[libreriscv.git] / Cesar_Strauss.mdwn

diff --git a/Cesar_Strauss.mdwn b/Cesar_Strauss.mdwn
index fa2b1fb7c98731d1db712191dfa26ae0ac56db87..e1ca0783d5d8abdbb206262230adb835691a4c17 100644 (file)
--- a/Cesar_Strauss.mdwn
+++ b/Cesar_Strauss.mdwn
@@ -50,19 +50,56 @@ unit tests.
        <https://bugs.libre-soc.org/show_bug.cgi?id=350>  
        Priority: Medium-ish
 
-9. FSM-based ALU example needed (compliant with ALU CompUnit)  
-       <https://bugs.libre-soc.org/show_bug.cgi?id=417>  
-       Status: DONE  
-       Investigating one last optimization opportunity.  
-       Priority: Low
-       
-10. Find root cause of cxxsim hang  
-       <https://bugs.libre-soc.org/show_bug.cgi?id=475#c2>  
-       Status: ongoing  
-       Priority: High
+11. Formal Proof for CompUnit  
+        <https://bugs.libre-soc.org/show_bug.cgi?id=342>
+
+12. Formal Proof for PartitionedSignal  
+        <https://bugs.libre-soc.org/show_bug.cgi?id=565>  
+        Status: in progress  
+
+13. Implement simple VL for-loop in nMigen for TestIssuer  
+        <https://bugs.libre-soc.org/show_bug.cgi?id=583>  
+        Status: in progress  
 
 ## Completed but not yet submitted:
 
+1. FSM-based ALU example needed (compliant with ALU CompUnit)  
+       <https://bugs.libre-soc.org/show_bug.cgi?id=417>  
+
+2. Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder  
+       <https://bugs.libre-soc.org/show_bug.cgi?id=600>
+
 ## Submitted for NLNet RFP
 
+### NLnet.2019.02.012
+
+* [Bug #583](https://bugs.libre-soc.org/show_bug.cgi?id=583):
+  Implement simple VL for\-loop in nMigen for TestIssuer
+    * &euro;2325 which is the total amount
+    * submitted on 2022-06-16
+
+### NLNet.2019.10.032.Formal
+
+* [Bug #565](https://bugs.libre-soc.org/show_bug.cgi?id=565):
+  Improve formal verification on PartitionedSignal
+    * &euro;2200 out of total of &euro;3000
+    * submitted on 2022-06-16
+
+### NLNet.2019.10.046.Standards
+
+* [Bug #588](https://bugs.libre-soc.org/show_bug.cgi?id=588):
+  add SVP64 to PowerDecoder2
+    * &euro;300 out of total of &euro;1000
+    * submitted on 2022-06-16
+
 ## Paid
+
+### NLNet.2019.10.043.Wishbone
+
+* [Bug #475](https://bugs.libre-soc.org/show_bug.cgi?id=475):
+  cxxsim improvements
+    * Ran several Libre-SOC tests under cxxsim
+    * Helped isolate simulator issues by extracting a MVCE
+(Minimal, Verifiable, Complete Example) in each case.
+    * paid on 2021-05-11
+    * &euro;250 out of total of &euro;1750