bug 1034: making room for crfbinlog/crfternlogi/crbinlog/crternlogi

[libreriscv.git] / Cesar_Strauss.mdwn

diff --git a/Cesar_Strauss.mdwn b/Cesar_Strauss.mdwn
index 940d91d2b610d1467b76ccf2b855b0403d2a9370..e1ca0783d5d8abdbb206262230adb835691a4c17 100644 (file)
--- a/Cesar_Strauss.mdwn
+++ b/Cesar_Strauss.mdwn
@@ -50,11 +50,6 @@ unit tests.
        <https://bugs.libre-soc.org/show_bug.cgi?id=350>  
        Priority: Medium-ish
 
-10. Find root cause of cxxsim hang  
-       <https://bugs.libre-soc.org/show_bug.cgi?id=475#c2>  
-       Status: ongoing  
-       Priority: High
-
 11. Formal Proof for CompUnit  
         <https://bugs.libre-soc.org/show_bug.cgi?id=342>
 
@@ -76,9 +71,30 @@ unit tests.
 
 ## Submitted for NLNet RFP
 
+### NLnet.2019.02.012
+
+* [Bug #583](https://bugs.libre-soc.org/show_bug.cgi?id=583):
+  Implement simple VL for\-loop in nMigen for TestIssuer
+    * &euro;2325 which is the total amount
+    * submitted on 2022-06-16
+
+### NLNet.2019.10.032.Formal
+
+* [Bug #565](https://bugs.libre-soc.org/show_bug.cgi?id=565):
+  Improve formal verification on PartitionedSignal
+    * &euro;2200 out of total of &euro;3000
+    * submitted on 2022-06-16
+
+### NLNet.2019.10.046.Standards
+
+* [Bug #588](https://bugs.libre-soc.org/show_bug.cgi?id=588):
+  add SVP64 to PowerDecoder2
+    * &euro;300 out of total of &euro;1000
+    * submitted on 2022-06-16
+
 ## Paid
 
-### NLNet.2019.10.Wishbone
+### NLNet.2019.10.043.Wishbone
 
 * [Bug #475](https://bugs.libre-soc.org/show_bug.cgi?id=475):
   cxxsim improvements