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[libreriscv.git] / HDL_workflow / HyperRAM.mdwn

diff --git a/HDL_workflow/HyperRAM.mdwn b/HDL_workflow/HyperRAM.mdwn
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   <https://ftp.libre-soc.org/W956x8MBYA_64Mb_HyperBus_pSRAM_TFBGA24_datasheet_A01-005_20211208.pdf>
 * Winbond Verilog Model for W956A8MBY:
   <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
-* VHDL hyperram <https://github.com/MJoergen/HyperRAM>
 
 ```
 from nmigen.resources.memory import HyperRAMResources