add --disable-svp64 to litex sim build

[soc.git] / Makefile

diff --git a/Makefile b/Makefile
index 453d0a472441cd6b8845faa64528ab4fda4db7a0..20fe492187474443575dfca71efe2fe25a01b2b1 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -13,12 +13,18 @@ mkpinmux:
 
 install: develop mkpinmux
 
+pywriter:
+       python3 src/soc/decoder/pseudo/pywriter.py
+
+svanalysis:
+       python3 libreriscv/openpower/sv_analysis.py
+
 develop:
-       python3 setup.py develop --user # yes, develop, not install
+       python3 setup.py develop # yes, develop, not install
        python3 src/soc/decoder/pseudo/pywriter.py
 
 run_sim: install
-       python3 src/soc/simple/issuer_verilog.py \
+       python3 src/soc/simple/issuer_verilog.py --disable-svp64\
                        src/soc/litex/florent/libresoc/libresoc.v
        python3 src/soc/litex/florent/sim.py --cpu=libresoc
 
@@ -32,7 +38,7 @@ testgpio_run_sim:
 ls180_verilog:
        python3 src/soc/simple/issuer_verilog.py \
                --debug=jtag --enable-core --enable-pll \
-               --enable-xics --enable-sram4x4kblock
+               --enable-xics --enable-sram4x4kblock --disable-svp64
                        src/soc/litex/florent/libresoc/libresoc.v
 
 test: install