whoops Makefile error
[soc.git] / Makefile
index a0530bffb6f169acc2d24b3d04b91ea4fccd8997..25b6135237a37318dbe5e80290633ecdbe2d705c 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,13 +1,46 @@
 PYTHON3 ?= "python3"
 
+.PHONY: help Makefile gitupdate install run_sim test htmlupload
+
 gitupdate:
        git submodule init
-       git submodule update --recursive
+       git submodule update --init --recursive --remote
+
+mkpinmux:
+       ./mkpinmux.sh
+       cp pinmux/ls180/ls180_pins.py src/soc/debug
+       cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc
+
+install: develop mkpinmux
+
+pywriter:
+       python3 src/soc/decoder/pseudo/pywriter.py
 
-install:
+svanalysis:
+       python3 libreriscv/openpower/sv_analysis.py
+
+develop:
        python3 setup.py develop # yes, develop, not install
        python3 src/soc/decoder/pseudo/pywriter.py
 
+run_sim:
+       python3 src/soc/simple/issuer_verilog.py --disable-svp64\
+                       src/soc/litex/florent/libresoc/libresoc.v
+       python3 src/soc/litex/florent/sim.py --cpu=libresoc
+
+testgpio_run_sim:
+       python3 src/soc/simple/issuer_verilog.py \
+                       src/soc/litex/florent/libresoc/libresoc.v \
+                       --enable-testgpio
+       python3 src/soc/litex/florent/sim.py --cpu=libresoc \
+                       --variant=standardjtagtestgpio
+
+ls180_verilog:
+       python3 src/soc/simple/issuer_verilog.py \
+               --debug=jtag --enable-core --enable-pll \
+               --enable-xics --enable-sram4x4kblock --disable-svp64 \
+                       src/soc/litex/florent/libresoc/libresoc.v
+
 test: install
        python3 setup.py test # could just run nosetest3...
 
@@ -25,8 +58,6 @@ BUILDDIR      = build
 help:
        @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
 
-.PHONY: help Makefile
-
 # Catch-all target: route all unknown targets to Sphinx using the new
 # "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
 %: Makefile