Synchronize LVT state, completing the induction proof

[soc.git] / Makefile

diff --git a/Makefile b/Makefile
index 20bce282fdd9dc00c6ecea00bb78c6061dcb72f8..8d379590387090fa04a28b2b64ebac56c26231ec 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -56,9 +56,23 @@ ls180_4k_verilog:
                --enable-xics --enable-sram4x4kblock --disable-svp64 \
                        src/soc/litex/florent/libresoc/libresoc.v
 
-# build microwatt "external core"
+# build microwatt "external core", note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
 microwatt_external_core:
-       python3 simple/issuer_verilog.py --microwatt-compat --enable-mmu \
+       python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
+            external_core_top.v
+
+microwatt_external_core_spi:
+       python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+            --enable-mmu \
+            --pc-reset 0x10000000 \
+            external_core_top.v
+
+microwatt_external_core_bram:
+       python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+            --enable-mmu \
+            --pc-reset 0xFF000000 \
             external_core_top.v
 
 # build the litex libresoc SoC without 4k SRAMs