cp pinmux/ls180/ls180_pins.py src/soc/debug
cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc
-install: gitupdate develop mkpinmux svanalysis
+install: gitupdate develop mkpinmux
+# this is now actually part of openpower-isa repository
pywriter:
- python3 src/soc/decoder/pseudo/pywriter.py
+ echo "pywriter is part of openpower-isa, run that instead"
+# this is now actually part of openpower-isa repository
svanalysis:
- python3 libreriscv/openpower/sv_analysis.py
+ echo "sv_analysis is part of openpower-isa, run that instead"
develop:
python3 setup.py develop # yes, develop, not install
python3 src/soc/litex/florent/sim.py --cpu=libresoc \
--variant=standardjtagtestgpio
+ls180_verilog_nopll:
+ python3 src/soc/simple/issuer_verilog.py \
+ --debug=jtag --enable-core --disable-pll \
+ --enable-xics --disable-svp64 \
+ src/soc/litex/florent/libresoc/libresoc.v
+
ls180_verilog:
python3 src/soc/simple/issuer_verilog.py \
--debug=jtag --enable-core --enable-pll \
--enable-xics --enable-sram4x4kblock --disable-svp64 \
src/soc/litex/florent/libresoc/libresoc.v
+# build microwatt "external core", note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
+microwatt_external_core:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
+ external_core_top.v
+
+microwatt_external_core_spi:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+ --enable-mmu \
+ --pc-reset 0x10000000 \
+ external_core_top.v
+
# build the litex libresoc SoC without 4k SRAMs
ls180_verilog_build: ls180_verilog
make -C soc/soc/litex/florent ls180
test: install
python3 setup.py test # could just run nosetest3...
+pypiupload:
+ $(PYTHON3) setup.py sdist upload
+
# Minimal makefile for Sphinx documentation
#