-
+
+# Preamble
+
+* Preamble not part of the submission
+* [[SEP-210803722 Libre-SOC 8 core/discussion]] see additional notes
+* Public copy of submission posted through europa.eu
+* <https://ec.europa.eu/info/funding-tenders/opportunities/portal/screen/opportunities/topic-details/horizon-cl4-2021-digital-emerging-01-01>
+* Annex also submitted (NLnet)
+* With much thanks and gratitude to everyone who provided crucial
+ input and feedback, especially on such short notice.
+* With many thanks to the EU for this opportunity.
+
# SEP-210803722 Libre-SOC 8 core
List of participants
|----- |------------- |--------------------- |--------- |------------- |
| 1 |David Calderwood |RED Semiconductor Ltd |UK |1/RED |
| 2 |Luke Leighton |The Libre-SOC Project |Netherlands |2/Libre-SOC |
-| 3 |Céline Ghibaudo |Sorbonne Université (LIP6 Lab) |France |3/SU |
-| 4 |Céline Ghibaudo |Sorbonne Université (CNRS Lab) |France |4/CNRS |
+| 3 |Marie-Minervé Louerat |Sorbonne Université (LIP6 Lab) |France |3/SU |
+| 4 |Marie-Minervé Louerat |Sorbonne Université (CNRS Lab) |France |4/CNRS |
| 5 |Michiel Lenaars |NLnet |Netherlands |5/NLnet |
| 6 |James Lewis |Helix Technology Ltd |UK |6/Helix |
Set Architecture (ISA) of the past sixty years. With NLnet's help we have
TRL (3) implementations and simulations demonstrating a 75% reduction in
the program size of core algorithms for Video and Audio DSP Processing
-(FFT, DCT, Matrix Multiply), and these still need optimized, which if
+(FFT, DCT, Matrix Multiply), and these still have room for optimisation,
+which if
successfully expanded to general-purpose algorithms would result in huge
power savings if deployed in mass-volume end-user products.
it to lower geometries and larger ASIC sizes which will be critical to
European businesses' Digital and Silicon Sovereignty.
- For the avoidance of confusion the use of the word "Cell" refers to a
+For the avoidance of confusion the use of the word "Cell" refers to a
bounded piece of electronic design that when used together, like bricks,
form larger more complicated electrical functions.
- To help advance Digital Sovereignty, LIP6 and CNRS need to once
+To help advance Digital Sovereignty, LIP6 and CNRS need to once
again push the boundaries of the Libre/Open VLSI toolchain, coriolis2
Place-and-Route, https://coriolis2.lip6.fr and HITAS/YAGLE Static Timing
Analyser https://www-soc.lip6.fr/equipe-cian/logiciels/tasyagle/ both
Chips4Makers (also NLnet funded) created FlexLib Libre/Open Cell
Libraries which allows porting of Standard Cell Libraries to any geometry.
An NDA'd TSMC 180nm version of FlexLib was created for the Libre-SOC
-180nm test ASIC. To achieve our objectives, LIP6 and CNRS will need to
+180nm test ASIC. To achieve our objectives, RED Semiconductor,
+Libre-SOC, LIP6 and CNRS will need to
create smaller geometry ports of FlexLib. These Cell Libraries need to
be tested in actual Silicon, and consequently we will be working with
IMEC as a sub-contractor and partner to deliver MPW Shuttle Runs for
* Targeted applications: We are developing a general-purpose Hybrid Architecture suitable for 3D, Video, Digital Signal Processing, Cryptographic applications, AI and many more. As it is general-purpose it covers all these areas. However in certain areas "specialist" instructions are needed (particularly 3D) and we seek additional funding to complete them. This includes Helix's high-accuracy GPS application which qualifies as a step-improvement in "Sensor fusion".
* Hardware-software co-design and Libre/Open Hardware-Software: as all participants are trained as Software Engineers, we inherently and automatically bring Software Engineering practices and techniques to Hardware design, and consequently achieve a far greater effectiveness and flexibility. Additionally, all participants are long-term contributors to Libre/Open Software and Hardware Projects. This shall continue throughout this Grant proposal. The involvement of RED Semiconductor Ltd brings further semiconductor hardware experience, bringing balance to the overall team.
* Moore's Law and changing Economics: as a general-purpose Cray-style Vector Supercomputer ISA, what we are designing may deploy either "Fast and Narrow" back-end (internal) micro-architecture, or "Slow and Wide": huge numbers of SIMD ALUs running at a much slower clock rate. The beauty and elegance of a Vector ISA is that, unlike SIMD ISAs such as AVX-512, NEON and to a partial extend SVE2, is that the programmer doesn't need to know about the internal micro-architecture, but their programs achieve the same throughput, even on larger geometries.
-* Hardware-based security: We consider it deeply unwise to follow the false practice of "adding more complexity to achieve more security". Security is achieved through simplicity and transparency. Simplicity: we studied historic Supercomputer designs dating back to 1965 (CDC 6600) where pure pragmatism required simpler and more elegant designs. Transparency: Fully Libre/Open designs that customers can themselves verify by running Formal Correctness Proofs (where those tools are also Libre/Open Source). Fully Libre/Open VLSI toolchains and Cell Libraries (no possibility of insertion of spying at the Silicon level). "Tripwires" embedded into the silicon to gauge area-local EMF "Signatures". Additionally, we already have work underway into Out-of-Order Execution and seek to explore Speculative Execution Mitigation techniques at the hardware level, to increase security. These are practical achievable demonstrable ways to achieve Hardware-based trust.
+* Hardware-based security: We consider it deeply unwise to follow the false practice of "adding more complexity to achieve more security". Security is achieved through simplicity and transparency. Simplicity: we studied historic Supercomputer designs dating back to 1965 (CDC 6600) where pure pragmatism required simpler and more elegant designs,
+and with Mitch Alsup's help learned how to bring them up-to-date.
+Transparency: Fully Libre/Open designs that customers can themselves verify by running Formal Correctness Proofs (where those tools are also Libre/Open Source). Fully Libre/Open VLSI toolchains and Cell Libraries (no possibility of insertion of spying at the Silicon level). "Tripwires" embedded into the silicon to gauge area-local EMF "Signatures". Additionally, we already have work underway into Out-of-Order Execution and seek to explore Speculative Execution Mitigation techniques at the hardware level, to increase security. These are practical achievable demonstrable ways to achieve Hardware-based trust.
* Security and Safety-critical Guidelines: Due to our overall approach, although potentially inherently achievable by others utilising our work as the basis for ongoing Research, the main participants consider it out of scope due to practical time constraints. Security Certification typically takes 5 to 7 years: The scope of this project is only 3. NLnet however may fund work that does indeed take into account these criteria.
* ASIC (Chip) prototyping: We are developing RTL including High-Level (core designs) as well as Low-Level (Cell Libraries). Nobody in any European Company will use a Cell Library if it has not been demonstrated as Silicon-Proven. As we already did with the 180nm ASIC, the best way to prove that a Cell Library (and an innovative approach - using Libre/Open VLSI toolchains) works is to do an actual ASIC.
# 3 Quality and efficiency of the implementation
-
-https://online.visual-paradigm.com/diagrams/tutorials/pert-chart-tutorial/
-
-
Work Packages:
# 3.1 Work plan and resources
+[[!img 2021-10-19_09-50.png size="550px" ]]
+
Tables for section 3.1
## Table 3.1d: List of milestones
+List of Milestones:
|M/stone #|Milestone name |WP# |Due date |Means of verification |
|------ | ------ | ----- | ------ | ------ |
| |Cost EUR |Justification |
| ------ | ----- | ------ |
|travel / subst |48000 |3yr World-wide travel to conferences/meetings/interviews |
-|equipment |140000 |High-end Servers for Layouts, High-end FPGAs for testing |
+|equipment |240000 |High-end Servers for Layouts, High-end FPGAs for testing, Jigs |
|Other/Good/work/Svc. |90000 |Legal/Accountancy/Insurance +prof. business services |
|remaining purch. cst. | | |
-|Total |278000 | |
+|Total |378000 | |
### Table 3.1h: 2/Libre-SOC Purchase costs
projects / libreriscv.git / blobdiff