(no commit message)

[libreriscv.git] / Samuel_A_Falvo_II.mdwn

diff --git a/Samuel_A_Falvo_II.mdwn b/Samuel_A_Falvo_II.mdwn
index a1d14345e4149b76b13eadc77f07c12072645fe7..ed0275bebb480763d07bb221bd14c2a9a2f04990 100644 (file)
--- a/Samuel_A_Falvo_II.mdwn
+++ b/Samuel_A_Falvo_II.mdwn
@@ -12,12 +12,18 @@ Move things along from one stage to the next.
 
 ## Currently working on
 
- - <https://bugs.libre-soc.org/show_bug.cgi?id=340> formal proof of POWER9 SHIFTROT pipeline needed
+* <https://bugs.libre-soc.org/show_bug.cgi?id=340>
+  - formal proof of POWER9 SHIFTROT pipeline needed
 
 ## Completed but not yet submitted:
 
- - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR pipeline formal correctness proof needed
- - <https://bugs.libre-soc.org/show_bug.cgi?id=421> TRAP pipeline formal correctness proof needed
+* <https://bugs.libre-soc.org/show_bug.cgi?id=418>
+  - SPR pipeline formal correctness proof needed
+  - EUR 350 (shared with [[lkcl]]
+* <https://bugs.libre-soc.org/show_bug.cgi?id=421>
+  - TRAP pipeline formal correctness proof needed
+* <https://bugs.libre-soc.org/show_bug.cgi?id=419>
+  - MUL pipeline formal proof needed
 
 ## Submitted (but not confirmed paid) for NLNet RFP