# Date: 21.4.2017
# Description: Translation Lookaside Buffer, SV39
# fully set-associative
+
+Implementation in c++:
+https://raw.githubusercontent.com/Tony-Hu/TreePLRU/master/TreePLRU.cpp
+
+Text description:
+https://people.cs.clemson.edu/~mark/464/p_lru.txt
"""
from math import log2
from nmigen import Signal, Module, Cat, Const, Array
from nmigen.lib.coding import Encoder
from ptw import TLBUpdate, PTE, ASID_WIDTH
+from plru import PLRU
+from tlb_content import TLBContent
-TLB_ENTRIES = 4
-
-
-class TLBEntry:
- def __init__(self):
- self.asid = Signal(ASID_WIDTH)
- # SV39 defines three levels of page tables
- self.vpn0 = Signal(9)
- self.vpn1 = Signal(9)
- self.vpn2 = Signal(9)
- self.is_2M = Signal()
- self.is_1G = Signal()
- self.valid = Signal()
-
- def flatten(self):
- return Cat(*self.ports())
-
- def eq(self, x):
- return self.flatten().eq(x.flatten())
-
- def ports(self):
- return [self.asid, self.vpn0, self.vpn1, self.vpn2,
- self.is_2M, self.is_1G, self.valid]
-
-
-class TLBContent:
- def __init__(self):
- self.flush_i = Signal() # Flush signal
- # Update TLB
- self.update_i = TLBUpdate()
- self.vpn2 = Signal(9)
- self.vpn1 = Signal(9)
- self.vpn0 = Signal(9)
- self.lu_hit = Signal() # to replacement logic
- self.replace_en = Signal() # replace the following entry,
- # set by replacement strategy
- # Lookup signals
- self.lu_asid_i = Signal(ASID_WIDTH)
- self.lu_content_o = PTE()
- self.lu_is_2M_o = Signal()
- self.lu_is_1G_o = Signal()
- self.lu_hit_o = Signal()
-
- def elaborate(self, platform):
- m = Module()
-
- tags = TLBEntry()
- content = PTE()
-
- m.d.comb += self.lu_hit.eq(0)
- # temporaries for 1st level match
- asid_ok = Signal()
- vpn2_ok = Signal()
- tags_ok = Signal()
- vpn2_hit = Signal()
- m.d.comb += [tags_ok.eq(tags.valid),
- asid_ok.eq(tags.asid == self.lu_asid_i),
- vpn2_ok.eq(tags.vpn2 == self.vpn2),
- vpn2_hit.eq(tags_ok & asid_ok & vpn2_ok)]
- # temporaries for 2nd level match
- vpn1_ok = Signal()
- tags_2M = Signal()
- vpn0_ok = Signal()
- vpn0_or_2M = Signal()
- m.d.comb += [vpn1_ok.eq(self.vpn1 == tags.vpn1),
- tags_2M.eq(tags.is_2M),
- vpn0_ok.eq(self.vpn0 == tags.vpn0),
- vpn0_or_2M.eq(tags_2M | vpn0_ok)]
- # first level match, this may be a giga page,
- # check the ASID flags as well
- with m.If(vpn2_hit):
- # second level
- with m.If (tags.is_1G):
- m.d.sync += self.lu_content_o.eq(content)
- m.d.comb += [ self.lu_is_1G_o.eq(1),
- self.lu_hit_o.eq(1),
- self.lu_hit.eq(1),
- ]
- # not a giga page hit so check further
- with m.Elif(vpn1_ok):
- # this could be a 2 mega page hit or a 4 kB hit
- # output accordingly
- with m.If(vpn0_or_2M):
- m.d.sync += self.lu_content_o.eq(content)
- m.d.comb += [ self.lu_is_2M_o.eq(tags.is_2M),
- self.lu_hit_o.eq(1),
- self.lu_hit.eq(1),
- ]
-
- # ------------------
- # Update and Flush
- # ------------------
-
- replace_valid = Signal()
- m.d.comb += replace_valid.eq(self.update_i.valid & self.replace_en)
- with m.If (self.flush_i):
- # invalidate (flush) conditions: all if zero or just this ASID
- with m.If (self.lu_asid_i == Const(0, ASID_WIDTH) |
- (self.lu_asid_i == tags.asid)):
- m.d.sync += tags.valid.eq(0)
-
- # normal replacement
- with m.Elif(replace_valid):
- m.d.sync += [ # update tag array
- tags.asid.eq(self.update_i.asid),
- tags.vpn2.eq(self.update_i.vpn[18:27]),
- tags.vpn1.eq(self.update_i.vpn[9:18]),
- tags.vpn0.eq(self.update_i.vpn[0:9]),
- tags.is_1G.eq(self.update_i.is_1G),
- tags.is_2M.eq(self.update_i.is_2M),
- tags.valid.eq(1),
- # and content as well
- content.eq(self.update_i.content)
- ]
-
- return m
-
- def ports(self):
- return [self.flush_i,
- self.lu_asid_i,
- self.lu_is_2M_o, self.lu_is_1G_o, self.lu_hit_o,
- ] + self.update_i.content.ports() + self.update_i.ports()
-
+TLB_ENTRIES = 8
class TLB:
def __init__(self):
self.flush_i = Signal() # Flush signal
- # Update TLB
- self.update_i = TLBUpdate()
# Lookup signals
self.lu_access_i = Signal()
self.lu_asid_i = Signal(ASID_WIDTH)
self.lu_is_2M_o = Signal()
self.lu_is_1G_o = Signal()
self.lu_hit_o = Signal()
+ # Update TLB
+ self.pte_width = len(self.lu_content_o.flatten())
+ self.update_i = TLBUpdate()
def elaborate(self, platform):
m = Module()
#-------------
# Translation
#-------------
+
+ # SV39 defines three levels of page tables
m.d.comb += [ vpn0.eq(self.lu_vaddr_i[12:21]),
vpn1.eq(self.lu_vaddr_i[21:30]),
vpn2.eq(self.lu_vaddr_i[30:39]),
]
- # SV39 defines three levels of page tables
tc = []
for i in range(TLB_ENTRIES):
- tlc = TLBContent()
+ tlc = TLBContent(self.pte_width, ASID_WIDTH)
setattr(m.submodules, "tc%d" % i, tlc)
tc.append(tlc)
+ # connect inputs
+ tlc.update_i = self.update_i # saves a lot of graphviz links
m.d.comb += [tlc.vpn0.eq(vpn0),
tlc.vpn1.eq(vpn1),
tlc.vpn2.eq(vpn2),
tlc.flush_i.eq(self.flush_i),
- tlc.update_i.eq(self.update_i),
- tlc.lu_asid_i.eq(self.lu_asid_i)
- ]
-
+ #tlc.update_i.eq(self.update_i),
+ tlc.lu_asid_i.eq(self.lu_asid_i)]
tc = Array(tc)
+ #--------------
+ # Select hit
+ #--------------
+
# use Encoder to select hit index
+ # XXX TODO: assert that there's only one valid entry (one lu_hit)
hitsel = Encoder(TLB_ENTRIES)
- m.submodules += hitsel
+ m.submodules.hitsel = hitsel
hits = []
for i in range(TLB_ENTRIES):
- hits.append(tc[i].lu_hit)
- m.d.comb += hitsel.i.eq(Cat(*hits))
+ hits.append(tc[i].lu_hit_o)
+ m.d.comb += hitsel.i.eq(Cat(*hits)) # (goes into plru as well)
idx = hitsel.o
- active = Signal()
+ active = Signal(reset_less=True)
m.d.comb += active.eq(~hitsel.n)
with m.If(active):
+ # active hit, send selected as output
m.d.comb += [ self.lu_is_1G_o.eq(tc[idx].lu_is_1G_o),
self.lu_is_2M_o.eq(tc[idx].lu_is_2M_o),
self.lu_hit_o.eq(1),
- self.lu_content_o.eq(tc[idx].lu_content_o)
+ self.lu_content_o.flatten().eq(tc[idx].lu_content_o),
]
- # -----------------------------------------------
- # PLRU - Pseudo Least Recently Used Replacement
- # -----------------------------------------------
-
- TLBSZ = 2*(TLB_ENTRIES-1)
- plru_tree = Signal(TLBSZ)
+ #--------------
+ # PLRU.
+ #--------------
- # The PLRU-tree indexing:
- # lvl0 0
- # / \
- # / \
- # lvl1 1 2
- # / \ / \
- # lvl2 3 4 5 6
- # / \ /\/\ /\
- # ... ... ... ...
- # Just predefine which nodes will be set/cleared
- # E.g. for a TLB with 8 entries, the for-loop is semantically
- # equivalent to the following pseudo-code:
- # unique case (1'b1)
- # lu_hit[7]: plru_tree[0, 2, 6] = {1, 1, 1};
- # lu_hit[6]: plru_tree[0, 2, 6] = {1, 1, 0};
- # lu_hit[5]: plru_tree[0, 2, 5] = {1, 0, 1};
- # lu_hit[4]: plru_tree[0, 2, 5] = {1, 0, 0};
- # lu_hit[3]: plru_tree[0, 1, 4] = {0, 1, 1};
- # lu_hit[2]: plru_tree[0, 1, 4] = {0, 1, 0};
- # lu_hit[1]: plru_tree[0, 1, 3] = {0, 0, 1};
- # lu_hit[0]: plru_tree[0, 1, 3] = {0, 0, 0};
- # default: begin /* No hit */ end
- # endcase
- LOG_TLB = int(log2(TLB_ENTRIES))
- for i in range(TLB_ENTRIES):
- # we got a hit so update the pointer as it was least recently used
- hit = Signal()
- m.d.comb += hit.eq(tc[i].lu_hit & self.lu_access_i)
- with m.If(hit):
- # Set the nodes to the values we would expect
- for lvl in range(LOG_TLB):
- idx_base = (1<<lvl)-1
- # lvl0 <=> MSB, lvl1 <=> MSB-1, ...
- shift = LOG_TLB - lvl;
- new_idx = Const(~((i >> (shift-1)) & 1), 1)
- print ("plru", i, lvl, hex(idx_base),
- idx_base + (i >> shift), shift, new_idx)
- m.d.sync += plru_tree[idx_base + (i >> shift)].eq(new_idx)
+ p = PLRU(TLB_ENTRIES)
+ m.submodules.plru = p
- # Decode tree to write enable signals
- # Next for-loop basically creates the following logic for e.g.
- # an 8 entry TLB (note: pseudo-code obviously):
- # replace_en[7] = &plru_tree[ 6, 2, 0]; #plru_tree[0,2,6]=={1,1,1}
- # replace_en[6] = &plru_tree[~6, 2, 0]; #plru_tree[0,2,6]=={1,1,0}
- # replace_en[5] = &plru_tree[ 5,~2, 0]; #plru_tree[0,2,5]=={1,0,1}
- # replace_en[4] = &plru_tree[~5,~2, 0]; #plru_tree[0,2,5]=={1,0,0}
- # replace_en[3] = &plru_tree[ 4, 1,~0]; #plru_tree[0,1,4]=={0,1,1}
- # replace_en[2] = &plru_tree[~4, 1,~0]; #plru_tree[0,1,4]=={0,1,0}
- # replace_en[1] = &plru_tree[ 3,~1,~0]; #plru_tree[0,1,3]=={0,0,1}
- # replace_en[0] = &plru_tree[~3,~1,~0]; #plru_tree[0,1,3]=={0,0,0}
- # For each entry traverse the tree. If every tree-node matches
- # the corresponding bit of the entry's index, this is
- # the next entry to replace.
+ # connect PLRU inputs/outputs
+ # XXX TODO: assert that there's only one valid entry (one replace_en)
+ en = []
for i in range(TLB_ENTRIES):
- en = Signal(LOG_TLB)
- for lvl in range(LOG_TLB):
- idx_base = (1<<lvl)-1
- # lvl0 <=> MSB, lvl1 <=> MSB-1, ...
- shift = LOG_TLB - lvl;
- new_idx = (i >> (shift-1)) & 1;
- plru = Signal()
- m.d.comb += plru.eq(plru_tree[idx_base + (i>>shift)])
- # en &= plru_tree_q[idx_base + (i>>shift)] == new_idx;
- if new_idx:
- m.d.comb += en[lvl].eq(~plru) # yes inverted (using bool())
- else:
- m.d.comb += en[lvl].eq(plru) # yes inverted (using bool())
- print ("plru", i, en)
- # boolean logic manipluation:
- # plur0 & plru1 & plur2 == ~(~plru0 | ~plru1 | ~plru2)
- m.d.sync += tc[i].replace_en.eq(~Cat(*en).bool())
+ en.append(tc[i].replace_en_i)
+ m.d.comb += [Cat(*en).eq(p.replace_en_o), # output from PLRU into tags
+ p.lu_hit.eq(hitsel.i),
+ p.lu_access_i.eq(self.lu_access_i)]
#--------------
# Sanity checks
projects / soc.git / blobdiff