re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / about_us.mdwn

diff --git a/about_us.mdwn b/about_us.mdwn
index b5ac4e4adf686648b12c2208c58055788cd7f75a..34a4b5e70458dfc0b72f09f6a9886938a1bc65d4 100644 (file)
--- a/about_us.mdwn
+++ b/about_us.mdwn
@@ -89,12 +89,6 @@ Alain's website: <http://phcomp.co.uk>
 * Digital circuit design
 * Availability: Outside normal working hours.
 
-## [[Cole Poirier|cole]]
-
-* Trying to learn and organize stuff
-* GitHub: [[https://github.com/colepoirier]]
-* Availability: full-time
-
 ## [[Sanjay A Menon|Sanjay]]
 
 * Skills: Verilog, C/C++, Python, TCL & PERL
@@ -137,11 +131,21 @@ Alain's website: <http://phcomp.co.uk>
 * Availability:  10+hrs/week, more is negotiable
 * Timezone:  UTC-07:00 (DST UTC-06:00, 2nd Sun of Mar-1st Sun of Nov)
 
+## [[Dmitry Selyutin|ghostmansd]]
+
+* Interests: OS development, fishing, classical antiquity
+* Languages: C, C++, Python
+* FW experience: system programming
+* Availability: depends on a week (0..10+hrs/week)
+
 ## Object Automation
 
 ### [[oa/madan]]
 
-TODO
+* Interests: Programming in Python and Knowledge of ML algorithms and NLP
+* Availability: 5 hours per week
+* Statistician
+
 
 ### [[oa/gautham]]
 
@@ -151,13 +155,66 @@ TODO
 
 ### [[oa/adithya]]
 
-TODO, Adithya
+* Interests:Digital System Design,PCB layout, Programming, Machine Learning, IoT
+* Programming Languages: Verilog, C, C++, Java, Python3, Julia
+* Availability: ~10hrs per week
+
+### [[oa/Niranjan]]
+
+* Interests: Digital System Design, PCB Layout, Programming
+* Programming Languages: Verilog, C, C++, Python
+* Availability: ~8-10 hours/week
+
+### [[oa/Abhishek]]
+
+* Interests: HPC, embedded systems, Digital system design 
+* Programming Languages: C, Python, Java, VHDL
+* Availability: ~8-10 hours/week
+
+### [[oa/Sukhanshu D]]
+
+* Experience: SOC Verification Intern, Digital Design
+* Programming Languages: Python, Verilog, Ng-spice
+* Availability: 4-6 hours per week
+
+### [[oa/Mehul N]]
+
+* Interests: Digital Design, Verification, IC Fabrication
+* Programming Languages: Verilog, System Verilog, UVM
+* Availability: ~ 6-8 hours/week
+* Experience: SoC Verification Intern, Research Intern at KIS
 
 ## 3mdeb
 
-### [[3mdeb/ghostmansd]]
+## [[Kyle Lehman|klehman]]
 
-* Interests: OS development, fishing, classical antiquity
-* Languages: C, C++, Python
-* FW experience: system programming
-* Availability: depends on a week (0..10+hrs/week)
+* Languages: C/C++, Java, Python, SQL, assembly
+* Interests: Language design, microacrhitecture, OS design, emulation, 3D computation 
+* Other interests: Nearly anything that floats, flies, or has an engine with wheels
+
+## [[Andrey Miroshnikov|andreym]]
+* Languages: C, Python, Verilog, Shell script
+* Interests: Analogue/digital electronics, RF, mobile comms, compilers, FPGAs, discrete mathematics, microarchitecture, Unix OSs, PCB design
+* Experience: FPGA/ASIC system validation, instrument automation using VISA, PCB design (KiCAD, Altium)
+* Other interests: King James Bible, Russian Synodal Bible, Languages, Philosophy, History
+* Availability: Full-time
+* IRC: octavius
+
+## [[Manikandan Nagarajan|Manik]]
+
+* Languages: Verilog HDL, VHDL, C, Python & TCL
+* Experience : Domain Specific Architecture Design and Implementation, IP Core Development, System on Chip, FPGA System Design, Chip Tapeout, Crypto Chip Design, Authentication Protocol Design. 
+* LinkedIn Profile: [[https://www.linkedin.com/in/manikandan-nagarajan-2156171a0/]]
+* Availability: 8~10hrs/week
+
+## [[Toshaan Bharvani|toshywoshy]]
+* Languages: C, C++, Golang, Python, Ruby, Assembly, Java, Javascript, bash, ksh, ...
+* Interests: Software on optimized hardware, compilers, FPGAs, microarchitecture, Unix OSs, Linux, Enterprise Software
+* Experience: Software, Firmware, BIOS/UEFI, Microcode, Services
+* Other interests: History, Mechanics, Tinkering
+* Availability: Full-time
+* IRC: toshywoshy
+
+## Former Members
+
+### [[Cole Poirier|cole]]