re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / about_us.mdwn

diff --git a/about_us.mdwn b/about_us.mdwn
index c74ced180bbb51f458ca3487a68dc27ced42a840..34a4b5e70458dfc0b72f09f6a9886938a1bc65d4 100644 (file)
--- a/about_us.mdwn
+++ b/about_us.mdwn
@@ -89,12 +89,6 @@ Alain's website: <http://phcomp.co.uk>
 * Digital circuit design
 * Availability: Outside normal working hours.
 
-## [[Cole Poirier|cole]]
-
-* Trying to learn and organize stuff
-* GitHub: [[https://github.com/colepoirier]]
-* Availability: full-time
-
 ## [[Sanjay A Menon|Sanjay]]
 
 * Skills: Verilog, C/C++, Python, TCL & PERL
@@ -137,16 +131,12 @@ Alain's website: <http://phcomp.co.uk>
 * Availability:  10+hrs/week, more is negotiable
 * Timezone:  UTC-07:00 (DST UTC-06:00, 2nd Sun of Mar-1st Sun of Nov)
 
-## [[Mikolaj Wielgus|mikolajw]]
+## [[Dmitry Selyutin|ghostmansd]]
 
-* Interests: Libre software and hardware, analog circuits, RF and microwave circuits, nonlinear systems, oscillators
-* Hardware Experience: PCB schematic and layout design, very small amount of IC design
-* Software Experience: Data acquisition and processing (LXI, SCPI), GUI development (wxWidgets), Microcontroller programming (AVR, STM32), video game development (Love2D, SDL)
-* Languages: Verilog, Asm (AVR), C, C++, C#, D, Python, Octave, Lua, Java, or any other language involving a similar set of abstractions
-* GitLab: https://gitlab.com/mwielgus
-* Most of my skills are self-taught by making small amateur projects. I have only little industry experience.
-* Availability: ~6 hrs/week
-* Timezone: UTC+01:00
+* Interests: OS development, fishing, classical antiquity
+* Languages: C, C++, Python
+* FW experience: system programming
+* Availability: depends on a week (0..10+hrs/week)
 
 ## Object Automation
 
@@ -196,13 +186,6 @@ Alain's website: <http://phcomp.co.uk>
 
 ## 3mdeb
 
-### [[Dmitry Selyutin|3mdeb/ghostmansd]]
-
-* Interests: OS development, fishing, classical antiquity
-* Languages: C, C++, Python
-* FW experience: system programming
-* Availability: depends on a week (0..10+hrs/week)
-
 ## [[Kyle Lehman|klehman]]
 
 * Languages: C/C++, Java, Python, SQL, assembly
@@ -210,15 +193,28 @@ Alain's website: <http://phcomp.co.uk>
 * Other interests: Nearly anything that floats, flies, or has an engine with wheels
 
 ## [[Andrey Miroshnikov|andreym]]
-* Languages: C, Python, Verilog
+* Languages: C, Python, Verilog, Shell script
 * Interests: Analogue/digital electronics, RF, mobile comms, compilers, FPGAs, discrete mathematics, microarchitecture, Unix OSs, PCB design
 * Experience: FPGA/ASIC system validation, instrument automation using VISA, PCB design (KiCAD, Altium)
-* Other interests: Lingua Latina, Philosophy, History
+* Other interests: King James Bible, Russian Synodal Bible, Languages, Philosophy, History
 * Availability: Full-time
+* IRC: octavius
 
 ## [[Manikandan Nagarajan|Manik]]
 
-* Languages: Verilog HDL, C, Python & TCL
+* Languages: Verilog HDL, VHDL, C, Python & TCL
 * Experience : Domain Specific Architecture Design and Implementation, IP Core Development, System on Chip, FPGA System Design, Chip Tapeout, Crypto Chip Design, Authentication Protocol Design. 
 * LinkedIn Profile: [[https://www.linkedin.com/in/manikandan-nagarajan-2156171a0/]]
 * Availability: 8~10hrs/week
+
+## [[Toshaan Bharvani|toshywoshy]]
+* Languages: C, C++, Golang, Python, Ruby, Assembly, Java, Javascript, bash, ksh, ...
+* Interests: Software on optimized hardware, compilers, FPGAs, microarchitecture, Unix OSs, Linux, Enterprise Software
+* Experience: Software, Firmware, BIOS/UEFI, Microcode, Services
+* Other interests: History, Mechanics, Tinkering
+* Availability: Full-time
+* IRC: toshywoshy
+
+## Former Members
+
+### [[Cole Poirier|cole]]