sync_up: Formatting fixes

[libreriscv.git] / about_us.mdwn

diff --git a/about_us.mdwn b/about_us.mdwn
index 93ff1aec139cb1878242cf9abe7009b326dc1036..5eaeef9426c53f990e863aee2309177aa600d144 100644 (file)
--- a/about_us.mdwn
+++ b/about_us.mdwn
@@ -51,7 +51,7 @@ Also, check out [[The_Mission]].
   compression, signal processing (sound & picture), optimisations,
   design for test...
 
-## Lauri Kasanen
+## [[Lauri Kasanen|lauri]]
 
 * Embedded software engineer
 * Interests: niche platforms, embedded, servers, graphics
@@ -89,12 +89,6 @@ Alain's website: <http://phcomp.co.uk>
 * Digital circuit design
 * Availability: Outside normal working hours.
 
-## [[Cole Poirier|cole]]
-
-* Trying to learn and organize stuff
-* GitHub: [[https://github.com/colepoirier]]
-* Availability: full-time
-
 ## [[Sanjay A Menon|Sanjay]]
 
 * Skills: Verilog, C/C++, Python, TCL & PERL
@@ -136,3 +130,107 @@ Alain's website: <http://phcomp.co.uk>
 * Website:  [[https://launchpad.net/~richard-wilbur]]
 * Availability:  10+hrs/week, more is negotiable
 * Timezone:  UTC-07:00 (DST UTC-06:00, 2nd Sun of Mar-1st Sun of Nov)
+
+## [[Dmitry Selyutin|ghostmansd]]
+
+* Interests: OS development, fishing, classical antiquity
+* Languages: C, C++, Python
+* FW experience: system programming
+* Availability: depends on a week (0..10+hrs/week)
+
+## [[Kyle Lehman|klehman]]
+
+* Languages: C/C++, Java, Python, SQL, assembly
+* Interests: Language design, microacrhitecture, OS design, emulation, 3D computation 
+* Other interests: Nearly anything that floats, flies, or has an engine with wheels
+
+## [[Andrey Miroshnikov|andreym]]
+* Languages: C, Python, Verilog, Shell script
+* Interests: Analogue/digital electronics, RF, mobile comms, compilers,
+FPGAs, discrete mathematics, microarchitecture, Unix OSs, PCB design
+* Experience: FPGA/ASIC system validation, instrument automation using
+VISA, PCB design (KiCAD, Altium)
+* Other interests: King James Bible, Russian Synodal Bible, Languages,
+Philosophy, History, Orienteering
+* Availability: Mon-Fri 8am-6pm UTC, Sat-Sun intermittent
+* IRC: octavius | [email](mailto:andrey at technepisteme.xyz)
+
+## [[Manikandan Nagarajan|Manik]]
+
+* Languages: Verilog HDL, VHDL, C, Python & TCL
+* Experience : Domain Specific Architecture Design and Implementation, IP Core Development, System on Chip, FPGA System Design, Chip Tapeout, Crypto Chip Design, Authentication Protocol Design. 
+* LinkedIn Profile: [[https://www.linkedin.com/in/manikandan-nagarajan-2156171a0/]]
+* Availability: 8~10hrs/week
+
+## [[Toshaan Bharvani|toshywoshy]]
+* Languages: C, C++, Golang, Python, Ruby, Assembly, Java, JavaScript, bash, ksh, ...
+* Interests: Software on optimized hardware, compilers, FPGAs, microarchitecture, Unix OSs, Linux, Enterprise Software
+* Experience: Software, Firmware, BIOS/UEFI, Microcode, Services
+* Other interests: History, Mechanics, Tinkering
+* Availability: Full-time
+* IRC: toshywoshy
+
+## [[Sadoon Albader|sadoon]]
+* Computer engineer specializing in hardware design
+* Home system administrator
+* Knowledge in Debian, Gentoo, and Arch
+* Languages: C, VHDL, SystemVerilog
+* Built my own (now unmaintained) powerpc and ppc64 ports for Debian 11, now working on [Debian 12](https://libre-soc.org/SFFS/debian_bootstrap/) and [Gentoo](https://libre-soc.org/SFFS/gentoo_bootstrap/) POWER9 SFFS
+* Experience: Intel FPGA design, HDL optimization, Software to HDL conversion (SPP), Microprocessor Architecture
+* Other Interests: Religion, History, Automobiles
+* Website: [[https://albader.co]]
+* Availability: Tuesdays & Wednesdays 3-8PM UTC, Friday ~12-8PM UTC
+
+## [[Shriya Sharma|shriya]]
+* TODO
+
+## Object Automation
+
+### [[oa/madan]]
+
+* Interests: Programming in Python and Knowledge of ML algorithms and NLP
+* Availability: 5 hours per week
+* Statistician
+
+### [[oa/gautham]]
+
+* Interests: Digital System Design, PCB Layout, Programming, Machine Learning
+* Programming Languages: Verilog, C, C++, Python
+* Availability: ~8-10 hours/week
+
+### [[oa/adithya]]
+
+* Interests:Digital System Design,PCB layout, Programming, Machine Learning, IoT
+* Programming Languages: Verilog, C, C++, Java, Python3, Julia
+* Availability: ~10hrs per week
+
+### [[oa/Niranjan]]
+
+* Interests: Digital System Design, PCB Layout, Programming
+* Programming Languages: Verilog, C, C++, Python
+* Availability: ~8-10 hours/week
+
+### [[oa/Abhishek]]
+
+* Interests: HPC, embedded systems, Digital system design 
+* Programming Languages: C, Python, Java, VHDL
+* Availability: ~8-10 hours/week
+
+### [[oa/Sukhanshu D]]
+
+* Experience: SOC Verification Intern, Digital Design
+* Programming Languages: Python, Verilog, Ng-spice
+* Availability: 4-6 hours per week
+
+### [[oa/Mehul N]]
+
+* Interests: Digital Design, Verification, IC Fabrication
+* Programming Languages: Verilog, System Verilog, UVM
+* Availability: ~ 6-8 hours/week
+* Experience: SoC Verification Intern, Research Intern at KIS
+
+## 3mdeb
+
+## Former Members
+
+### [[Cole Poirier|cole]]