re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / andreym.mdwn

diff --git a/andreym.mdwn b/andreym.mdwn
index f4252a0a79a8821f5e364a1459bec53de6d3a8b2..683430c2a072cf23a5341efbbb2c54f9529f0d55 100644 (file)
--- a/andreym.mdwn
+++ b/andreym.mdwn
@@ -19,8 +19,19 @@
 
 ## Submitted to NLNet but not yet paid
 
-### NLnet.2019.02
+### NLNet.2019.10.046.Standards
+
+* [Bug #858](https://bugs.libre-soc.org/show_bug.cgi?id=858):
+  SVP64 Primer Documentation
+    * submitted on 2022-06-27
+    * €1500 out of total of €3000
+
+### NLNet.2019.10.031.Video
 
+* [Bug #865](https://bugs.libre-soc.org/show_bug.cgi?id=865):
+  implement vector bitmanip opcodes
+    * submitted on 2022-06-26
+    * €1000 out of total of €3500
 
 ## Paid by NLNet