add cesar

[libreriscv.git] / cole.mdwn

diff --git a/cole.mdwn b/cole.mdwn
index c2f1c258da36243682f187e6013142c31cae10a7..2fe174ee3fd9fa4e4d30d50437e9456706189f0b 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -1,6 +1,6 @@
 # Cole Poirier
 
-Apprentice and assistant Project coordinator for Libre-SOC
+Former Apprentice at Libre-SOC
 
 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
 
@@ -42,21 +42,28 @@ move things along from one stage to the next
 
 ## Completed but not yet submitted
 
-- <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI JTAG TAP needed
-  - EUR 150
-
 ## Submitted for NLNet RFP
 
 submitted but not confirmed paid:
 
-# MOU coriolis2 2019-10-029, submitted on 2020-DEC-06
+## Paid
+
+### MOU coriolis2 2019-10-029, received payment on 2021-MAY-5
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=502> determine SRAM block size and implement it 
+  - EUR 50
+
+### MOU wishbone 2019-10-043, received payment on 2021-MAY-5
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI JTAG TAP needed
+  - EUR 150
+
+### MOU coriolis2 2019-10-029, received payment on 2020-DEC-20
 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=178> Coriolis2 tutorial
   - EUR 500
 
-## Paid
-
-# MOU wishbone 2019-10-043, recieved payment on 2020-OCT-01
+### MOU wishbone 2019-10-043, received payment on 2020-OCT-01
 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
   - EUR 150
@@ -73,7 +80,7 @@ submitted but not confirmed paid:
 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
   - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
 
-# MOU coriolis2 2019-10-029, recieved payment on 2020-OCT-01
+### MOU coriolis2 2019-10-029, received payment on 2020-OCT-01
 
 - Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
   - <https://bugs.libre-soc.org/show_bug.cgi?id=291>