set clock freq Constant length to 32-bit in Tercel.

[soc.git] / conf.py

diff --git a/conf.py b/conf.py
index 881c95e2be8804f3b048b35667782d0fbebd9551..12b29a4fb10659843b17c069255fcc3199cc77ba 100644 (file)
--- a/conf.py
+++ b/conf.py
@@ -174,9 +174,13 @@ texinfo_documents = [
 
 # -- Options for intersphinx extension ---------------------------------------
 
+lsocbase = 'https://docs.libre-soc.org/'
 # Example configuration for intersphinx: refer to the Python standard library.
 intersphinx_mapping = {"python": ('https://docs.python.org/3', None),
-                       "nmigen": ('https://nmigen.info/nmigen', 'latest')
+                       "nmigen": ('https://nmigen.info/nmigen', 'latest'),
+                       "openpower": (lsocbase+'openpower-isa', None),
+                       #"nmutil": (lsocbase+'nmutil', None),
+                       #"ieee754fpu": (lsocbase+'ieee754fpu', None),
                       }
 
 # -- Options for todo extension ----------------------------------------------