% Copyright 2024 Jacob Lifshay
-\documentclass[slidestop]{beamer}
+\documentclass{beamer}
\usepackage{beamerthemesplit}
\usetheme{default}
\usepackage[english]{babel}
+\usepackage{tikz}
+\usepackage{minted}
+\usemintedstyle{monokai}
+\definecolor{codebg}{rgb}{0.1,0.09,0.08}
+\newminted[codeenv]{python3}{escapeinside=@@,fontsize=\small,bgcolor=codebg}
+\newmintinline[codeinline]{python3}{escapeinside=@@,fontsize=\small,bgcolor=codebg}
-\title[]{
+\title[Fast Big-Integer Arithmetic on SVP64 ...]{
Fast Big-Integer Arithmetic on SVP64 at up to 256-bits/cycle and beyond
}
\titlepage
\end{frame}
+\begin{frame}[fragile]
+ \frametitle{What is SVP64?}
+ \begin{itemize}
+ \item Vectorization Extension for PowerISA developed by \href{https://libre-soc.org}{Libre-SOC}
+ \pause
+ \item Basically, a way to modify nearly any PowerISA instruction to run it in a HW loop.
+ \pause \\
+ \medskip
+ Simple Example:
+ \begin{codeenv}
+setvl 0, 0, 3, 0, 1, 1 # makes stuff run 3 times
+sv.add *r3, *r15, r12 # adds 3 times
+@\pause@
+# expands to:
+add r3, r15, r12 # no * means r12 doesn't increment
+add r4, r16, r12 # * means r3 and r15 increment
+add r5, r17, r12
+ \end{codeenv}
+ \end{itemize}
+\end{frame}
+
+\begin{frame}[fragile]
+ \frametitle{Big-Integer Addition on SVP64}
+ How can we use SVP64 to add 256-bit integers?
+ \pause
+ \begin{codeenv}
+setvl 0, 0, 4, 0, 1, 1 # makes stuff run 4 times
+addic r0, r0, 0 # clear CA (carry flag)
+sv.adde *r4, *r4, *r8 # carry-propagating add
+@\pause@
+# expands to:
+addic r0, r0, 0 # clear CA (carry flag)
+adde r4, r4, r8
+adde r5, r5, r9
+adde r6, r6, r10
+adde r7, r7, r11
+ \end{codeenv}
+\end{frame}
+
+\begin{frame}
+ \frametitle{Big-Integer Addition on an example CPU}
+ Disclaimer:
+ SVP64 is designed for everything from tiny to big and fast CPUs, this example only shows a hypothetical big and fast CPU design
+\end{frame}
+
+\begin{frame}
+ \frametitle{Big-Integer Addition on an example CPU}
+ \input{bigint-add-pipe.dia-tex}
+\end{frame}
+
+\begin{frame}[fragile]
+ \frametitle{Big-Integer Multiply on SVP64}
+ How can we use SVP64 to Multiply a 64-bit by a 256-bit integer?
+ \pause
+ \begin{itemize}
+ \item new instruction: \codeinline{maddedu RT, RA, RB, RC}
+ \pause
+ \item $64 \times 64 + 64 \rightarrow 128$-bit Multiply-Add
+ \pause
+ \item Semantics as used in this presentation (somewhat simplified):
+ \begin{codeenv}
+result = (RA * RB) + RC
+RT = LSB_HALF(result)
+RC = MSB_HALF(result)
+ \end{codeenv}
+ \end{itemize}
+\end{frame}
+
+\begin{frame}[fragile]
+ \frametitle{Big-Integer Multiply on SVP64}
+ How can we use SVP64 to Multiply a 64-bit by a 256-bit integer?
+ \pause
+ \begin{codeenv}
+# 64-bit input in r3
+# 256-bit input in r20-23
+# 320-bit output in r4-8
+setvl 0, 0, 4, 0, 1, 1 # makes stuff run 4 times
+li r8, 0 # clear carry register
+sv.maddedu *r4, r3, *r20, r8 # carrying multiply
+@\pause@
+# expands to:
+li r8, 0
+maddedu r4, r3, r20, r8
+maddedu r5, r3, r21, r8
+maddedu r6, r3, r22, r8
+maddedu r7, r3, r23, r8
+ \end{codeenv}
+\end{frame}
+
+\begin{frame}
+ \input{test.dia-tex}
+\end{frame}
+
\end{document}
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