add WIP 256-bit add frame

[libreriscv.git] / conferences / fosdem2024 / fosdem2024_bigint / fosdem2024_bigint.tex

diff --git a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
index a484c63e1b1bc23b97bdf300128d72df5f347385..832a8843014b557504a22191e8735c13abab7ae0 100644 (file)
--- a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
+++ b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
@@ -43,6 +43,35 @@ add r5, r17, r12
     \end{itemize}
 \end{frame}
 
+\begin{frame}[fragile]
+    \frametitle{Big-Integer Addition on SVP64}
+    How can we use SVP64 to add 256-bit integers?
+    \pause
+    \begin{semiverbatim}
+setvl 0, 0, 4, 0, 1, 1 # makes stuff run 4 times
+addic 0, 0, 0  # clear CA (carry flag)
+sv.adde *r4, *r4, *r8  # carry-propagating add
+\pause
+# expands to:
+addic 0, 0, 0  # clear CA (carry flag)
+adde r4, r4, r8
+adde r5, r5, r9
+adde r6, r6, r10
+adde r6, r6, r11
+    \end{semiverbatim}
+\end{frame}
+
+\begin{frame}
+    \frametitle{Big-Integer Addition on an example CPU}
+    Disclaimer:
+    SVP64 is designed for everything from tiny to big and fast CPUs, this example only shows a hypothetical big and fast CPU design
+\end{frame}
+
+\begin{frame}
+    \frametitle{Big-Integer Addition on an example CPU}
+    \input{bigint-add-pipe.dia-tex}
+\end{frame}
+
 \begin{frame}
     \input{test.dia-tex}
 \end{frame}