fosdem2024_bigint: add sv.maddedu diagram

[libreriscv.git] / conferences / fosdem2024 / fosdem2024_bigint / fosdem2024_bigint.tex

diff --git a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
index 79d1fd380d761a72788e3369490c8a7435c84813..f0efdaf7b7cab96d63138f22cae68ed32f331607 100644 (file)
--- a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
+++ b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
@@ -66,6 +66,13 @@ adde r7, r7, r11
     \end{codeenv}
 \end{frame}
 
+\begin{frame}[fragile]
+    \frametitle{Big-Integer Addition on SVP64}
+    How can we use SVP64 to add 256-bit integers?
+    \bigbreak
+    \input{sv.adde.dia-tex}
+\end{frame}
+
 \begin{frame}
     \frametitle{Big-Integer Addition on an example CPU}
     Disclaimer:
@@ -117,7 +124,8 @@ maddedu r7, r3, r23, r8
 \end{frame}
 
 \begin{frame}
-    \input{test.dia-tex}
+    \frametitle{Big-Integer Multiply on SVP64}
+    \input{sv.maddedu.dia-tex}
 \end{frame}
 
-\end{document}
\ No newline at end of file
+\end{document}