-%%\frame{\frametitle{Simple SBC-style SoC}
-%%
-%%\begin{center}
-%%\includegraphics[width=0.9\textwidth]{shakti_libre_soc.jpg}
-%%\end{center}
-
-%%}
-
-
-
-
\begin{frame}[fragile]
\frametitle{Simple-V CMPI in a nutshell}
\end{itemize}
\end{frame}
+
\frame{\frametitle{Load/Store Fault-First}
\begin{itemize}
\item Solution: a protocol that allows optional load/store
\item instruction \textit{requests} a number of elements
\item instruction \textit{informs} the number actually loaded
- \item first load/store is not optional
+ \item first element load/store is not optional (cannot fail)
+ \item ARM SVE: https://arxiv.org/pdf/1803.06185.pdf
+ \item more: wikipedia Vector processor page: Fault/Fail First
+ \vspace{10pt}
+ \item Load/Store is Memory to/from Register, what about
+ Register to Register?
+ \item Register-to-register: "Data-Dependent Fail-First."
+ \item Z80 LDIR: Mem-Register, CPIR: Register-Register
\end{itemize}
}
\begin{frame}[fragile]
- \frametitle{Data-Dependent Fail-First}
+ \frametitle{Data-Dependent-Fail-First in a nutshell}
\begin{semiverbatim}
- function op\_cmpi(BA, RA, SI) # cmpi not vector-cmpi!
- int i, id=0, ira=0;
- for (i = 0; i < VL; i++)
- CR[BA+id] <= compare(ireg[RA+ira], SI);
- if (reg\_is\_vectorised[BA] ) \{ id += 1; \}
- if (reg\_is\_vectorised[RA]) \{ ira += 1; \}
+function op\_cmpi(BA, RA, SI) # cmpi not vector-cmpi!
+int i, id=0, ira=0;
+for (i = 0; i < VL; i++)
+ CR[BA+id] <= compare(ireg[RA+ira], SI);
+ if (reg\_is\_vectorised[BA] ) \{ id += 1; \}
+ if (reg\_is\_vectorised[RA]) \{ ira += 1; \}
+ if test (CR[BA+id]) == FAIL: \{ VL = i + 1; break \}
\end{semiverbatim}
\begin{itemize}
- \item Above is oversimplified: predication etc. left out
- \item Scalar-scalar and scalar-vector and vector-vector now all in one
- \item OoO may choose to push CMPIs into instr. queue (v. busy!)
+ \item Parallelism still perfectly possible
+ ("hold" writing results until sequential post-analysis
+ carried out. Best done with OoO)
+ \item VL truncation can be inclusive or exclusive
+ (include or exclude a NULL pointer or a
+ string-end character, or overflow result)
+ \item \textit{Truncation can be to zero Vector Length}
\end{itemize}
\end{frame}
-
-\frame{\frametitle{Additional Simple-V features}
-
- \begin{itemize}
- \item "fail-on-first" (POWER9 VSX strncpy segfaults on boundary!)
- \item "Twin Predication" (covers VSPLAT, VGATHER, VSCATTER, VINDEX etc.)
- \item SVP64: extensive "tag" (Vector context) augmentation
- \item "Context propagation": a VLIW-like context. Allows contexts
- to be repeatedly applied.
- Effectively a "hardware compression algorithm" for ISAs.
- \item Ultimate goal: cut down I-Cache usage, cuts down on power
- \item Typical GPU has its own I-Cache and small shaders.\\
- \textit{We are a Hybrid CPU/GPU: I-Cache is not separate!}
- \item Needs to go through OpenPOWER Foundation `approval'
- \end{itemize}
-}
+\frame{\frametitle{Power ISA v3.1 vstribr}
+
+ \lstinputlisting[language={}]{vstribr.txt}
+
+ \begin{itemize}
+ \item ironically this hard-coded instruction is
+ identical to general-purpose Simple-V DD-FFirst...
+ \end{itemize}
+
+}Po
\frame{\frametitle{maxloc}
\begin{itemize}
\item "TODO
\end{itemize}
}
+
\frame{\frametitle{Pospopcount}
- \begin{semiverbatim}
- // Copyright (c) 2020 Robert Clausecker <fuz@fuz.su>
- // count8 reference implementation for tests. Do not alter.
- func count8safe(counts *[8]int, buf []uint8) {
- for i := range buf {
- for j := 0; j < 8; j++ {
- counts[j] += int(buf[i] >> j & 1)
- }
- }
- }
+
+ \begin{itemize}
+ \item Positional popcount adds up the totals of each bit set to 1 in each bit-position, of an array of input values.
+ \item Notoriously difficult to do in SIMD assembler: typically 550 lines
- A simple but still hardware-paralleliseable SVP64 assembler for 8-bit input values (count8safe) is as follows:
-
- mtspr 9, 3 # move r3 to CTR
- setvl 3,0,8,0,1,1 # set MVL=8, VL=r3=MIN(MVL,CTR)
- # load VL bytes (update r4 addr) but compressed (dw=8)
- addi 6, 0, 0 # initialise all 64-bits of r6 to zero
- sv.lbzu/pi/dw=8 *6, 1(4) # should be /lf here as well
- # gather performs the transpose (which gets us to positional..)
- gbbd 8,6
- # now those bits have been turned around, popcount and sum them
- setvl 0,0,8,0,1,1 # set MVL=VL=8
- sv.popcntd/sw=8 *24,*8 # do the (now transposed) popcount
- sv.add *16,*16,*24 # and accumulate in results
- # branch back if CTR still non-zero. works even though VL=8
- sv.bc/all 16, *0, -0x28 # reduce CTR by VL and stop if -ve
- \end{semiverbatim}
+ \end{itemize}
+
+ \lstinputlisting[language={}]{pospopcount.c}
+
+}
+
+\frame{\frametitle{Pospopcount}
+
+ \begin{center}
+ \includegraphics[width=0.5\textwidth]{pospopcount.png}
+ \end{center}
+
+}
+
+\frame{\frametitle{Pospopcount}
+
+ \begin{center}
+ \includegraphics[width=0.5\textwidth]{array_popcnt.png}
+ \end{center}
+
+ \begin{itemize}
+ \item Part of the challenge is therefore to perform an appropriate transpose of the data,
+ in blocks that suit the processor and the ISA capacity.
+ \item The gbbd instruction is used for implementing the transpose function,
+ preparing the data for using the standard popcount instruction.
+
+
+ \end{itemize}
+
+}
+
+\frame{\frametitle{Pospopcount.s}
+
+
+\lstinputlisting[language={}]{pospopcount.s}
}
+
\frame{\frametitle{strncpy}
+ \lstinputlisting[language={}]{strncpy.c}
\begin{itemize}
\item "TODO
\end{itemize}
}
+
+
\frame{\frametitle{strncpy assembler}
-\lstinputlisting[language={}]{\strncpy.s}
+\lstinputlisting[language={}]{strncpy.s}
}
projects / libreriscv.git / blobdiff