integer mul-add is MAC not FMAC

[libreriscv.git] / conferences / siliconsalon2023 / siliconsalon2023.tex

diff --git a/conferences/siliconsalon2023/siliconsalon2023.tex b/conferences/siliconsalon2023/siliconsalon2023.tex
index 63cdf6f5fcadd5129bf461fddbc8ac3c600a0a64..09782cb13448a02407e05c8b7d1f9352fd1cf4a1 100644 (file)
--- a/conferences/siliconsalon2023/siliconsalon2023.tex
+++ b/conferences/siliconsalon2023/siliconsalon2023.tex
@@ -139,10 +139,10 @@
 \begin{frame}[fragile]\frametitle{Vector-Scalar Multiply}
 
  \begin{itemize}
-   \item Normally in FMAC the top 64-bits is thrown away.
+   \item Normally in MAC the top 64-bits is thrown away.
    \item What if we stored those 64-bits in a 2nd register?\\
                (64-bit carry-out)
-   \item And what if the next FMAC added that "digit" on?\\
+   \item And what if the next MAC added that "digit" on?\\
                (64-bit carry-in)
    \item Again: a chain of these performs Vector-by-Scalar Multiply
   \end{itemize}