x86 insn is shld/shrd not dsld

[libreriscv.git] / conferences / siliconsalon2023 / siliconsalon2023.tex

diff --git a/conferences/siliconsalon2023/siliconsalon2023.tex b/conferences/siliconsalon2023/siliconsalon2023.tex
index 09782cb13448a02407e05c8b7d1f9352fd1cf4a1..cfd2a66d5de2a45ac44ca84ffa428d76fefb3609 100644 (file)
--- a/conferences/siliconsalon2023/siliconsalon2023.tex
+++ b/conferences/siliconsalon2023/siliconsalon2023.tex
@@ -241,7 +241,7 @@
 \begin{frame}[fragile]\frametitle{Draft Double-Shift}
 
  \begin{itemize}
-   \item Remarkably similar to x86 dsld
+   \item Remarkably similar to x86's shld/shrd
    \item Does not need 128-bit ROT: simple mod to existing hardware
    \item Hardware may macro-op fuse Vector-shift for better efficiency
    \item Chainable and in-place (no copy of vector needed).