re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / conferences.mdwn

diff --git a/conferences.mdwn b/conferences.mdwn
index 8dd1d586280eadcffa73370f269050181bb007d1..4ba25c5601262c59b51bf04ffcc37448b93b29b9 100644 (file)
--- a/conferences.mdwn
+++ b/conferences.mdwn
@@ -191,10 +191,7 @@ https://my.fsf.org/lp-call-for-sessions deadline dec 1 2021
 Wed, June 1, 2022   5:00 PM – 8:00 PM BST
 
 * <https://www.blockchaincommons.com/salons/silicon-salon/>
-* <https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/grev.py;hb=HEAD>
-* <https://libre-soc.org/openpower/isa/bitmanip/>
-* <https://libre-soc.org/openpower/sv/bitmanip/>
-* <https://libre-soc.org/openpower/sv/biginteger/analysis/>
+* [[conferences/siliconsalon2022]]
 
 ## XDC 2022