# Crypto-router ASIC
+<img src="https://www.ngi.eu/wp-content/uploads/sites/48/2020/04/Logo_Pointer.png" width="200px" />
+<img src="https://ngi.eu/wp-content/uploads/sites/77/2017/10/bandiera_stelle.png" width="50px" /><span> </span>
+<img src="https://nlnet.nl/image/logos/NGIAssure_tag.svg" width="130px" />
+<span> </span>
+<img src="https://www.artandtechnology.nl/logo.jpg" width="130px" />
+
+**This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-POINTER Project funded under grant agreement No 871528**
+
+**This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-ASSURE Project funded under grant agreement No 957073.**
+
* NLnet page: [[nlnet_2021_crypto_router]]
* Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
+* ASIC/IO Pin specification page: [[crypto_router_asic/crypto_router_pinspec]]
-# Specifications:
+# Specifications
-All of these are entirely Libre-Licensed:
+All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:
-* 300 mhz single-core, Libre-SOC OpenPOWER CPU
+* 300 mhz single-core,
+ [Libre-SOC](https://git.libre-soc.org/?p=soc.git;a=blob;f=README.md;hb=HEAD)
+ OpenPOWER CPU with
+ [[openpower/sv/bitmanip]] extensions
* 180/130 nm (TBD)
-* 5x [[RGMII]] Gigabit Ethernet PHYs
-* 2x USB [[ULPI]] PHYs
+* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs with
+ [SRAM](https://github.com/adamgreig/daqnet/blob/master/gateware/daqnet/ethernet/rmii.py)
+ on-chip, built-in.
+* 2x USB [[shakti/m_class/ULPI]] PHYs
* Direct DMA interface (independent bulk transfer)
-* JTAG, GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
+* [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
+ GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
* On-board Dual-ported SRAM (for Packet Buffers)
-* Opencores [[sdram]]
+* Opencores [[shakti/m_class/sdram]]
* Wishbone interfaces to all peripherals
-* XICS ICP / ICS Interrupt Controller
+* [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD)
+ Interrupt Controller
+
+
-# Example packet transfer:
+# Example packet transfer
* Packet comes in on RGMII port 1. Each PHY has its own dual-ported SRAM
* Packet is **directly** stored in internal (dual-ported SRAM) by
* Processor notifies target RGM-II PHY to activate "send" of frame out
through target RGM-II port 2.
+# Testing and Verification
+
+We will need full HDL simulations as well as post P&R simulations.
+These may be achieved as follows:
+
+* ISA-level unit tests as well as Formal Correctness Proofs.
+ Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
+ and individual unit tests for the
+ [Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
+* simulation
+ with some peripherals developed in c++ as verilator modules
+* nmigen-based OpenPOWER Libre-SOC core co-simulation such as
+ this unit test,
+ [test_issuer.py](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_issuer.py;hb=HEAD)
+* [cocotb pre/post PnR](https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=tree;f=ls180;hb=HEAD) including GHDL, Icarus and Verilator
+ (where best suited)
+
+Actual instructions being developed (bitmanip) may therefore be
+unit tested prior to deployment. Following that, rapid simulations
+may be achieved by running Litex (the same HDL may also easily
+be uploaded to an FPGA). When it comes to Place-and-Route of the
+ASIC, the cocotb simulations may be used to verify that the GDS-II
+layout has not been "damaged" by the PnR tools.
+
+Peripherals functionality tests must also be part of the simulations,
+particularly using cocotb, to ensure that they remain functional after PnR.
+Supercomputer access for compilation of verilator and/or cxxrtl is available
+through [[fed4fire]]
+
projects / libreriscv.git / blobdiff