Bug 1244: changes to images

[libreriscv.git] / crypto_router_asic.mdwn

diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn
index 6820f0c92a5d12d12c3f67579ce39ee67c336aaa..c877516d2e762d702700ff82ea5ec0bcb4c855f1 100644 (file)
--- a/crypto_router_asic.mdwn
+++ b/crypto_router_asic.mdwn
@@ -1,18 +1,31 @@
 # Crypto-router ASIC
 
+<img src="https://www.ngi.eu/wp-content/uploads/sites/48/2020/04/Logo_Pointer.png" width="200px" />
+<img src="https://ngi.eu/wp-content/uploads/sites/77/2017/10/bandiera_stelle.png" width="50px" /><span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span>
+<img src="https://nlnet.nl/image/logos/NGIAssure_tag.svg" width="130px" />
+<span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span>
+<img src="https://www.artandtechnology.nl/logo.jpg" width="130px" />
+
+**This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-POINTER Project funded under grant agreement No 871528**
+
+**This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-ASSURE Project funded under grant agreement No 957073.**
+
 * NLnet page: [[nlnet_2021_crypto_router]]
 * Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
+* ASIC/IO Pin specification page: [[crypto_router_asic/crypto_router_pinspec]]
 
-# Specifications:
+# Specifications
 
-All of these are entirely Libre-Licensed:
+All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:
 
 * 300 mhz single-core,
   [Libre-SOC](https://git.libre-soc.org/?p=soc.git;a=blob;f=README.md;hb=HEAD)
   OpenPOWER CPU with
   [[openpower/sv/bitmanip]] extensions
 * 180/130 nm (TBD)
-* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs
+* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs with
+  [SRAM](https://github.com/adamgreig/daqnet/blob/master/gateware/daqnet/ethernet/rmii.py)
+   on-chip, built-in.
 * 2x USB [[shakti/m_class/ULPI]] PHYs
 * Direct DMA interface (independent bulk transfer)
 * [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
@@ -23,7 +36,9 @@ All of these are entirely Libre-Licensed:
 * [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD)
   Interrupt Controller
 
-# Example packet transfer:
+
+
+# Example packet transfer
 
 * Packet comes in on RGMII port 1.  Each PHY has its own dual-ported SRAM
 * Packet is **directly** stored in internal (dual-ported SRAM) by
@@ -49,7 +64,7 @@ These may be achieved as follows:
   Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
   and individual unit tests for the
   [Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
-* [Litex sim.py](https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;hb=HEAD)
+* simulation
   with some peripherals developed in c++ as verilator modules
 * nmigen-based OpenPOWER Libre-SOC core co-simulation such as
   this unit test,
@@ -63,3 +78,9 @@ may be achieved by running Litex (the same HDL may also easily
 be uploaded to an FPGA).  When it comes to Place-and-Route of the
 ASIC, the cocotb simulations may be used to verify that the GDS-II
 layout has not been "damaged" by the PnR tools.
+
+Peripherals functionality tests must also be part of the simulations,
+particularly using cocotb, to ensure that they remain functional after PnR.
+Supercomputer access for compilation of verilator and/or cxxrtl is available
+through [[fed4fire]]
+