flesh out bigint add pipe slides

[libreriscv.git] / docs.mdwn

diff --git a/docs.mdwn b/docs.mdwn
index d0657e1d724ef34c66a8be396d6b6d7ef4e69051..18056542cac3ce42d96d8f435fe651e212b4c282 100644 (file)
--- a/docs.mdwn
+++ b/docs.mdwn
@@ -44,6 +44,7 @@ yourself, in order to verify them, see [[HDL_workflow]]
 * Pinmux and JTAG Boundary Scan [[docs/pinmux]]
 * pypowersim python-based command-line simulator [[docs/pypowersim]]
 * First steps [[docs/firststeps]]
+* Adding an instruction [[docs/adding_instr]] - see also below
 
 # SVP64
 
@@ -54,8 +55,7 @@ Supercomputing Cray-style Vectorisation of the Power ISA.
 
 TODO.  use the commit diffs for these instructions as a guide
 
-* fmvis <https://bugs.libre-soc.org/show_bug.cgi?id=887> which has
-  a very clean single-commit <https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=51ebd21c50d53275e8dd828a997433175b6dd2a2>
+* fmvis <https://bugs.libre-soc.org/show_bug.cgi?id=887>
 * avgadd etc. <https://bugs.libre-soc.org/show_bug.cgi?id=863>
 * int min/max <https://bugs.libre-soc.org/show_bug.cgi?id=234#c1>
 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745> which included