re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / docs.mdwn

diff --git a/docs.mdwn b/docs.mdwn
index e9918e64d9fd3db7304acba859314cfe4ad6de32..de8dceec05bb62d504699b2a96d45e298db5f024 100644 (file)
--- a/docs.mdwn
+++ b/docs.mdwn
@@ -33,23 +33,9 @@ The chroot is useful to ensure stability and repeatable builds: no
 errors or issues introduced by libraries being wrong versions.
 Also relevant is the [gdb gcc build](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=ppc64-gdb-gcc;hb=HEAD).
 
-    pip3 install virtualenv requests
-    mkdir ~/.virtualenvs && cd ~/.virtualenvs
-    python3 -m venv libresoc
-    source ~/.virtualenvs/libresoc/bin/activate
-    
-    cd ~; mkdir libresoc; cd libresoc
-    git clone https://git.libre-soc.org/git/nmutil.git
-    git clone https://git.libre-soc.org/git/openpower-isa.git
-    git clone https://git.libre-soc.org/git/c4m-jtag.git
-    git clone https://git.libre-soc.org/git/ieee754fpu.git
-    git clone https://git.libre-soc.org/git/soc.git
-    
-    cd nmutil; make develop; cd ..
-    cd openpower-isa; make develop pywriter svanalysis pyfnwriter; cd ..
-    cd c4m-jtag; make develop; cd ..
-    cd ieee754fpu; make develop; cd ..
-    cd soc; make gitupdate; make develop; cd ..
+For a simple set of commands to follow, see [[HDL_workflow/devscripts]]. If
+you prefer to do a manual install and explicitly install dependencies
+yourself, in order to verify them, see [[HDL_workflow]]
 
 ## Gtkwave Tutorial
 
@@ -63,3 +49,23 @@ Also relevant is the [gdb gcc build](https://git.libre-soc.org/?p=dev-env-setup.
 
 [[docs/learning_nmigen]]
 
+## Test API
+
+[[docs/testapi]]
+
+## Pinmux and JTAG Boundary Scan
+
+[[docs/pinmux]]
+
+## pypowersim python-based command-line simulator
+
+[[docs/pypowersim]]
+
+## First steps
+
+[[docs/firststeps]]
+
+## SVP64
+
+Currently in Draft form, [[openpower/sv/svp64]] is the basis of the
+Supercomputing Cray-style Vectorisation of the Power ISA.