add rv32um mulhu unit test

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index be324f3bd09d63ea274be28cac8be6f88e48f21e..18de70d98217ddc5fc7d0cbf3f89c3c1f0683202 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -1,3 +1,5 @@
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
 #define SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
   (reg0 | (reg1<<8) | (reg2<<8) | \
    (shape0<<24) | (shape0<<26) | (shape0<<28))
@@ -31,6 +33,10 @@
         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
         csrrw  x0, 0x4c0, x1
 
+#define SET_SV_CSR2( type, regkey, elwidth, regidx, isvec) \
+        li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
+        csrrw  x0, 0x4c1, x1
+
 #define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
         li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
         csrrw  x0, 0x4c8, x1
@@ -69,6 +75,10 @@
         la      x1, from; \
         flw     reg, offs(x1)
 
+#define TEST_SV_IMMW( reg, imm ) \
+        li      t6, MASK_XLEN(imm) ; \
+        bne     reg, t6, fail
+
 #define TEST_SV_IMM( reg, imm ) \
         li      t6, ((imm) & 0xffffffffffffffff); \
         bne     reg, t6, fail