add rv32um mulhu unit test

diff --git a/isa/Makefile b/isa/Makefile
index 8cdd3d509b7bdb5ead2a96543c7ac2d839994b7c..5c34d4e69ec42c66910cd7126803f5e4d666866f 100644 (file)
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -23,6 +23,7 @@ endif
 include $(src_dir)/rv32ui/Makefrag
 include $(src_dir)/rv32uc/Makefrag
 include $(src_dir)/rv32um/Makefrag
+include $(src_dir)/rv32um/Makefrag.sv
 include $(src_dir)/rv32ua/Makefrag
 include $(src_dir)/rv32uf/Makefrag
 include $(src_dir)/rv32ud/Makefrag

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index be324f3bd09d63ea274be28cac8be6f88e48f21e..18de70d98217ddc5fc7d0cbf3f89c3c1f0683202 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -1,3 +1,5 @@
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
 #define SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
   (reg0 | (reg1<<8) | (reg2<<8) | \
    (shape0<<24) | (shape0<<26) | (shape0<<28))
@@ -31,6 +33,10 @@
         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
         csrrw  x0, 0x4c0, x1
 
+#define SET_SV_CSR2( type, regkey, elwidth, regidx, isvec) \
+        li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
+        csrrw  x0, 0x4c1, x1
+
 #define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
         li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
         csrrw  x0, 0x4c8, x1
@@ -69,6 +75,10 @@
         la      x1, from; \
         flw     reg, offs(x1)
 
+#define TEST_SV_IMMW( reg, imm ) \
+        li      t6, MASK_XLEN(imm) ; \
+        bne     reg, t6, fail
+
 #define TEST_SV_IMM( reg, imm ) \
         li      t6, ((imm) & 0xffffffffffffffff); \
         bne     reg, t6, fail

diff --git a/isa/rv32um/Makefrag.sv b/isa/rv32um/Makefrag.sv
new file mode 100644 (file)
index 0000000..0797d9f
--- /dev/null
+++ b/isa/rv32um/Makefrag.sv
@@ -0,0 +1,11 @@
+#=======================================================================
+# Makefrag for rv32um tests
+#-----------------------------------------------------------------------
+
+rv32um_sv_tests = \
+       sv_mulhu_elwidth \
+
+rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sv_tests))
+rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sv_tests))
+
+spike32_tests += $(rv32um_p_tests) $(rv32um_v_tests)

diff --git a/isa/rv32um/sv_mulhu_elwidth.S b/isa/rv32um/sv_mulhu_elwidth.S
new file mode 100644 (file)
index 0000000..5d9f0a6
--- /dev/null
+++ b/isa/rv32um/sv_mulhu_elwidth.S
@@ -0,0 +1,90 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV32U        # Define TVM used by program.
+
+// TODO: add extra "code" argument and "testdata" argument,
+// replace "sraw" with "code"
+// TODO: move SV_ELWIDTH_TEST to sv_test_macros.h
+// TODO: probably remove testing of x15 and x16 (or pass in as extra args?)
+
+#define SV_ELWIDTH_TEST( vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+                         expect1, expect2, expect3 ) \
+                                                        \
+        SV_LD_DATA( x12, testdata   , 0);               \
+        SV_LD_DATA( x13, testdata+4 , 0);               \
+        SV_LD_DATA( x14, testdata+8, 0);               \
+        SV_LD_DATA( x15, testdata+12, 0);               \
+        SV_LD_DATA( x16, testdata+16, 0);               \
+        SV_LD_DATA( x17, testdata+20, 0);               \
+                                                        \
+        li x28, 0xa5a5a5a5;                                      \
+        li x29, 0xa5a5a5a5;                                      \
+        li x30, 0xa5a5a5a5;                                      \
+                                                        \
+        SET_SV_MVL( vl );                                  \
+        SET_SV_2CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1),       \
+                      SV_REG_CSR( 1, 12, wid2, 12, isvec2) );        \
+        SET_SV_CSR2( 1, 28, wid3, 28, isvec3);       \
+        SET_SV_VL( vl );                                   \
+                                                        \
+        mulhu   x28, x15, x12;                              \
+                                                        \
+        CLR_SV_CSRS();                                  \
+        SET_SV_VL( 1);                                   \
+        SET_SV_MVL( 1);                                  \
+                                                        \
+        TEST_SV_IMMW( x28, expect1 );                         \
+        TEST_SV_IMMW( x29, expect2 );                       \
+        TEST_SV_IMMW( x30, expect3 );                       
+
+
+# SV test: vector-vector add
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
+# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        # TODO: add "sraw" argument, add testdata argument
+        SV_ELWIDTH_TEST(  3, 0, 0, 0, 1, 1, 1,
+                0x7fffc000,  0x0001fefe,  0xfe010000 )
+/*
+        SV_ELWIDTH_TEST(  3, 0, 0, 3, 1, 1, 1,
+                0x0000008200000021,  0xa5a5a5a500000000,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  3, 1, 1, 0, 1, 1, 1,
+                0x9,  0x11,  0x19 )
+        SV_ELWIDTH_TEST(  3, 1, 1, 3, 1, 1, 1,
+                0x0000001100000009,  0xa5a5a5a500000019,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  3, 1, 1, 2, 1, 1, 1,
+                0xa5a5001900110009,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  3, 1, 1, 1, 1, 1, 1,
+                0xa5a5a5a5a5191109,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
+*/
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .word 0x80000000
+        .word 0xaaaaaaab
+        .word 0xff000000
+        .word 0xffff8000
+        .word 0x0002fe7d
+        .word 0xff000000
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+