from daniel benusovich, patch to move SV_ELWIDTH to sv_test_macros.h

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index f725de9e3561d74463ac30762fedbe9981f54e7f..1c7977c87aa4690b6fb7f144f9773cfb846619d3 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -29,6 +29,8 @@
         li     x1, SV_SHAPE_CSR( xd, yd, zd, offs, permute); \
         csrrw  x0, 0x4f8, x1
 
+// series of macros that set one, two or three register (or predicate)
+// key-value table entries that alter the behaviour of the registers
 #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
         csrrw  x0, 0x4c0, x1
@@ -53,10 +55,16 @@
         li     x1, c1 | ((c2)<<16U); \
         csrrw  x0, 0x4c8, x1
 
-#define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
+// clears the 2 CSRs set above
+#define CLR_SV_CSRS( ) csrrwi   x0, 0x4c0, 0xf;
 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
 
+// set maximum vector length.
 #define SET_SV_MVL( val ) csrrwi   x0, 0x4f1, (val-1)
+
+// set actual vector length: normally that would
+// be vl = xN = min(mvl, min(vl, xN) however we
+// pass in x0 here.
 #define SET_SV_VL( val )  csrrwi   x0, 0x4f0, (val-1)
 
 #define SV_LD_DATA( reg, from, offs ) \
@@ -101,6 +109,36 @@
         fmv.x.s x2, freg; \
         bne     x2, x1, fail;
 
+#define SV_ELWIDTH_TEST(code, testdata, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+                         expect1, expect2, expect3 )                   \
+                                                                       \
+        SV_LDD_DATA( x12, testdata   , 0);                             \
+        SV_LDD_DATA( x13, testdata+8 , 0);                             \
+        SV_LDD_DATA( x14, testdata+16, 0);                             \
+        SV_LDD_DATA( x15, testdata+24, 0);                             \
+        SV_LDD_DATA( x16, testdata+32, 0);                             \
+        SV_LDD_DATA( x17, testdata+40, 0);                             \
+                                                                               \
+        li x28, 0xa5a5a5a5a5a5a5a5;                                     \
+        li x29, 0xa5a5a5a5a5a5a5a5;                                     \
+        li x30, 0xa5a5a5a5a5a5a5a5;                                     \
+                                                                               \
+        SET_SV_MVL( vl );                                              \
+        SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1),            \
+                      SV_REG_CSR( 1, 12, wid2, 12, isvec2),            \
+                      SV_REG_CSR( 1, 28, wid3, 28, isvec3));           \
+        SET_SV_VL( vl );                                               \
+                                                                       \
+        code   x28, x15, x12;                                          \
+                                                                       \
+        CLR_SV_CSRS();                                                         \
+        SET_SV_VL( 1);                                                 \
+        SET_SV_MVL( 1);                                                \
+                                                                       \
+        TEST_SV_IMM( x28, expect1 );                                   \
+        TEST_SV_IMM( x29, expect2 );                                   \
+        TEST_SV_IMM( x30, expect3 );                                   \
+
 #define SV_W_DFLT 0
 #define SV_W_8BIT 1
 #define SV_W_16BIT 2