from daniel benusovich, patch to move SV_ELWIDTH to sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index 07c4e3dea00a8186688219f6b92bb5da7d7d4870..1c7977c87aa4690b6fb7f144f9773cfb846619d3 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -109,6 +109,36 @@
         fmv.x.s x2, freg; \
         bne     x2, x1, fail;
 
+#define SV_ELWIDTH_TEST(code, testdata, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+                         expect1, expect2, expect3 )                   \
+                                                                       \
+        SV_LDD_DATA( x12, testdata   , 0);                             \
+        SV_LDD_DATA( x13, testdata+8 , 0);                             \
+        SV_LDD_DATA( x14, testdata+16, 0);                             \
+        SV_LDD_DATA( x15, testdata+24, 0);                             \
+        SV_LDD_DATA( x16, testdata+32, 0);                             \
+        SV_LDD_DATA( x17, testdata+40, 0);                             \
+                                                                               \
+        li x28, 0xa5a5a5a5a5a5a5a5;                                     \
+        li x29, 0xa5a5a5a5a5a5a5a5;                                     \
+        li x30, 0xa5a5a5a5a5a5a5a5;                                     \
+                                                                               \
+        SET_SV_MVL( vl );                                              \
+        SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1),            \
+                      SV_REG_CSR( 1, 12, wid2, 12, isvec2),            \
+                      SV_REG_CSR( 1, 28, wid3, 28, isvec3));           \
+        SET_SV_VL( vl );                                               \
+                                                                       \
+        code   x28, x15, x12;                                          \
+                                                                       \
+        CLR_SV_CSRS();                                                         \
+        SET_SV_VL( 1);                                                 \
+        SET_SV_MVL( 1);                                                \
+                                                                       \
+        TEST_SV_IMM( x28, expect1 );                                   \
+        TEST_SV_IMM( x29, expect2 );                                   \
+        TEST_SV_IMM( x30, expect3 );                                   \
+
 #define SV_W_DFLT 0
 #define SV_W_8BIT 1
 #define SV_W_16BIT 2

diff --git a/isa/rv64ui/sv_addw_elwidth.S b/isa/rv64ui/sv_addw_elwidth.S
index f616794f581f11e267e5062f77c1b7ecb8eba4d8..7047ff0ef9060d521c3b8bb624b88a5bde5aa200 100644 (file)
--- a/isa/rv64ui/sv_addw_elwidth.S
+++ b/isa/rv64ui/sv_addw_elwidth.S
@@ -3,43 +3,6 @@
 
 RVTEST_RV64U        # Define TVM used by program.
 
-// TODO: add extra "code" argument and "testdata" argument,
-// replace "addw" with "code"
-// TODO: move SV_ELWIDTH_TEST to sv_test_macros.h
-// TODO: probably remove testing of x15 and x16 (or pass in as extra args?)
-
-#define SV_ELWIDTH_TEST( vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
-                         expect1, expect2, expect3 ) \
-                                                        \
-        SV_LDD_DATA( x12, testdata   , 0);               \
-        SV_LDD_DATA( x13, testdata+8 , 0);               \
-        SV_LDD_DATA( x14, testdata+16, 0);               \
-        SV_LDD_DATA( x15, testdata+24, 0);               \
-        SV_LDD_DATA( x16, testdata+32, 0);               \
-        SV_LDD_DATA( x17, testdata+40, 0);               \
-                                                        \
-        li x28, 0xa5a5a5a5a5a5a5a5;                                      \
-        li x29, 0xa5a5a5a5a5a5a5a5;                                      \
-        li x30, 0xa5a5a5a5a5a5a5a5;                                      \
-                                                        \
-        SET_SV_MVL( vl );                                  \
-        SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1),       \
-                      SV_REG_CSR( 1, 12, wid2, 12, isvec2),        \
-                      SV_REG_CSR( 1, 28, wid3, 28, isvec3));       \
-        SET_SV_VL( vl );                                   \
-                                                        \
-        addw   x28, x15, x12;                              \
-                                                        \
-        CLR_SV_CSRS();                                  \
-        SET_SV_VL( 1);                                   \
-        SET_SV_MVL( 1);                                  \
-                                                        \
-        TEST_SV_IMM( x28, expect1 );                         \
-        TEST_SV_IMM( x29, expect2 );                       \
-        TEST_SV_IMM( x30, expect3 );                       \
-        TEST_SV_IMM( x15, 0x0000005242322212);                       \
-        TEST_SV_IMM( x16, 0x0000005141312111);
-
 
 # SV test: vector-vector add
 #
@@ -50,35 +13,45 @@ RVTEST_RV64U        # Define TVM used by program.
 RVTEST_CODE_BEGIN   # Start of test code.
 
         # TODO: add "addw" argument, add testdata argument
-        SV_ELWIDTH_TEST(  3, 0, 0, 0, 1, 1, 1,
+        SV_ELWIDTH_TEST( addw, testdata, 3, 0, 0, 0, 1, 1, 1,
                 0xffffffff8b6bab8b,  0xffffffff88684828,  0x0000000000000000 )
-        SV_ELWIDTH_TEST(  3, 0, 0, 3, 1, 1, 1,
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 0, 0, 3, 1, 1, 1,
                 0x886848288b6bab8b,  0xa5a5a5a500000000,  0xa5a5a5a5a5a5a5a5 )
-        SV_ELWIDTH_TEST(  3, 1, 1, 0, 1, 1, 1,
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 1, 1, 0, 1, 1, 1,
                 0xffffffffffffff8b,  0xffffffffffffffab,  0x000000000000006b )
-        SV_ELWIDTH_TEST(  3, 1, 1, 3, 1, 1, 1,
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 1, 1, 3, 1, 1, 1,
                 0xffffffabffffff8b,  0xa5a5a5a50000006b,  0xa5a5a5a5a5a5a5a5 )
-        SV_ELWIDTH_TEST(  3, 1, 1, 2, 1, 1, 1,
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 1, 1, 2, 1, 1, 1,
                 0xa5a5006bffabff8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
-        SV_ELWIDTH_TEST(  3, 1, 1, 1, 1, 1, 1,
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 1, 1, 1, 1, 1, 1,
                 0xa5a5a5a5a56bab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
 
         # these test a scalar destination, for sign-extension on different
         # widths of source/dest.
-        SV_ELWIDTH_TEST(  3, 0, 0, 0, 1, 1, 0,
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 0, 0, 0, 1, 1, 0,
                 0xffffffff8b6bab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
-        SV_ELWIDTH_TEST(  3, 3, 3, 3, 1, 1, 0,
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 3, 3, 3, 1, 1, 0,
                 0xffffffff8b6bab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
-        SV_ELWIDTH_TEST(  3, 2, 2, 3, 1, 1, 0,
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 2, 2, 3, 1, 1, 0,
                 0xffffffffffffab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
-        SV_ELWIDTH_TEST(  3, 3, 2, 3, 1, 1, 0,
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 3, 2, 3, 1, 1, 0,
                 0x000000004232ab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
-        SV_ELWIDTH_TEST(  3, 2, 3, 3, 1, 1, 0,
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 2, 3, 3, 1, 1, 0,
                 0x000000004939ab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
 
+        # these test scalar sources, for sign-extension on different
+        # widths of source/dest.
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 0, 0, 0, 0, 1, 1,
+                0xffffffff8b6bab8b,  0xffffffff89694929,  0x0000000042322212 )
+        SV_ELWIDTH_TEST(  addw, testdata, 3, 0, 0, 3, 0, 1, 1,
+                0x896949298b6bab8b,  0xa5a5a5a542322212,  0xa5a5a5a5a5a5a5a5 )
+
+
+
         RVTEST_PASS           # Signal success.
 fail:
         RVTEST_FAIL
+
 RVTEST_CODE_END     # End of test code.
 
 # Input data section.