modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64uc / sv_c_mv.S

diff --git a/isa/rv64uc/sv_c_mv.S b/isa/rv64uc/sv_c_mv.S
index c85108ce8c548a2ece7836996343760af14ccace..ce8dd412a3e56572a7bca2b1f974f173f40da7a4 100644 (file)
--- a/isa/rv64uc/sv_c_mv.S
+++ b/isa/rv64uc/sv_c_mv.S
@@ -23,17 +23,17 @@ RVTEST_CODE_BEGIN   # Start of test code.
         li          x5, 0 # deliberately set x4 to 0
 
         SET_SV_MVL(3)
-        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),
-                      SV_REG_CSR(1, 6, 0, 6, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),
+                      SV_REG_CSR(1, 6, 0, 6, 1) )
         SET_SV_VL(3)
 
         .option rvc
         c.mv    x3, x6
         .option norvc
 
-        SET_SV_VL(0)
+        SET_SV_VL(1)
         CLR_SV_CSRS()
-        SET_SV_MVL(0)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(x3, 1001) # should not be modified
         TEST_SV_IMM(x4, 41)