modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64uc / sv_c_mv_predication.S

diff --git a/isa/rv64uc/sv_c_mv_predication.S b/isa/rv64uc/sv_c_mv_predication.S
index 3ad6535f586584b10151d5eda959632a066241a7..7345de0facb6800acd8eed103c0245e249392e99 100644 (file)
--- a/isa/rv64uc/sv_c_mv_predication.S
+++ b/isa/rv64uc/sv_c_mv_predication.S
@@ -17,20 +17,20 @@ RVTEST_RV64U        # Define TVM used by program.
         li          a4, pred2;                         \
                                                        \
         SET_SV_MVL(3);                                 \
-        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),    \
-                      SV_REG_CSR(1, 6, 0, 6, 1, 0) );  \
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),       \
+                      SV_REG_CSR(1, 6, 0, 6, 1) );     \
         SET_SV_2PREDCSRS(                              \
-                      SV_PRED_CSR(1, 3, 0, 0, 13, 1),  \
-                      SV_PRED_CSR(1, 6, 0, 0, 14, 1) );\
+                      SV_PRED_CSR(1, 3, 0, 0, 13, 0),  \
+                      SV_PRED_CSR(1, 6, 0, 0, 14, 0) );\
         SET_SV_VL(3);                                  \
                                                        \
         .option rvc;                                   \
         c.mv    x3, x6;                                \
         .option norvc;                                 \
                                                        \
-        SET_SV_VL(0);                                  \
+        SET_SV_VL(1);                                  \
         CLR_SV_CSRS();                                 \
-        SET_SV_MVL(0);                                 \
+        SET_SV_MVL(1);                                 \
                                                        \
         TEST_SV_IMM(x3, expect1);                      \
         TEST_SV_IMM(x4, expect2);                      \