modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64ud / sv_fadd.S

diff --git a/isa/rv64ud/sv_fadd.S b/isa/rv64ud/sv_fadd.S
index 9ef208271f6aff174e91e822209dd09bee9bd993..5818a2b8a59efe1c19faa446693b666e79d4bcb8 100644 (file)
--- a/isa/rv64ud/sv_fadd.S
+++ b/isa/rv64ud/sv_fadd.S
@@ -22,15 +22,15 @@ RVTEST_CODE_BEGIN   # Start of test code.
         SV_FLD_DATA( f8, testdata+56, 0)
 
         SET_SV_MVL(2)
-        SET_SV_2CSRS( SV_REG_CSR(0, 2, 0, 2, 1, 0),
-                      SV_REG_CSR(0, 6, 0, 6, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(0, 2, 0, 2, 1),
+                      SV_REG_CSR(0, 6, 0, 6, 1) )
         SET_SV_VL(2)
 
         fadd.d f2, f2, f6;
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_FD(0, f1, testdata+64, 0) 
         TEST_SV_FD(0, f2, testdata+72, 0)