modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64ui / sv_addi_scalar_src.S

diff --git a/isa/rv64ui/sv_addi_scalar_src.S b/isa/rv64ui/sv_addi_scalar_src.S
index 2d1e974acdcfd16d8def35142362a954fe983a10..edb0345febc8546daa14660aa5735e66c4437d1c 100644 (file)
--- a/isa/rv64ui/sv_addi_scalar_src.S
+++ b/isa/rv64ui/sv_addi_scalar_src.S
@@ -4,7 +4,9 @@
 RVTEST_RV64U        # Define TVM used by program.
 
 
-# SV test: sets up x6 data as a scalar, sets VL to 2, and carries out
+# SV test: scalar-to-vector add
+#
+# sets up x6 data as a scalar, sets VL to 2, and carries out
 # an "add 1 to x6 and store in x3".
 # which actually means:
 # "add add 1 to x6 and store in x3" *AND*
@@ -13,20 +15,20 @@ RVTEST_RV64U        # Define TVM used by program.
 # Test code region.
 RVTEST_CODE_BEGIN   # Start of test code.
 
-        SV_LD_DATA( x2, testdata   , 0)
-        SV_LD_DATA( x5, testdata+24, 0)
+        SV_LD_DATA( x2, testdata   , 0) # not expecting this to be modified
+        SV_LD_DATA( x5, testdata+24, 0) # not expecting this to be modified
 
-        li x6, 41
+        li x6, 41 # going to be stored in x3 *and* x4 (plus one, on each)
 
         SET_SV_MVL(2)
-        SET_SV_CSR(1, 3, 0, 3, 1, 0)
+        SET_SV_CSR(1, 3, 0, 3, 1)
         SET_SV_VL(2)
 
-        addi    x3, x6, 1
+        addi    x3, x6, 1 # x3 = x6+1 *AND* x4 = x6+1
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(x2, 1001) # should not be modified
         TEST_SV_IMM(x3, 42)