re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / lkcl.mdwn

diff --git a/lkcl.mdwn b/lkcl.mdwn
index 339d0ca0a63d7bf7a480f2af3be7593eb89d08b5..657c3791d569994153f3c354bfe287f0ec013412 100644 (file)
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -11,21 +11,46 @@ Lead dev and Project Coordinator for Libre-SOC.
 
 move things along from one stage to the next
 
+## Priority tasks to keep an eye on
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=195> Power ISA Formal Proof
+  EUR 6550
+* <https://bugs.libre-soc.org/show_bug.cgi?id=198> nmutil/etc Formal Proofs
+   EUR 8650
+* <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
+  EUR 5000
+
 ## Currently working on
 
  - Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
+   - EUR 1500
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
  - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
  - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
  - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
-  - EUR 150
+   - EUR 150
  - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
-  - EUR 150
+   - EUR 150
  - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
+   - EUR 1000
  - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
  - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
    - EUR 250
  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
-   - EUR 1250
+   - EUR 1000 of 1250 shared
  - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
  - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
  - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
@@ -43,7 +68,6 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
- - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer