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re-reserve bit in setvl -- needed for extending registers:
[libreriscv.git] / lkcl.mdwn
diff --git a/lkcl.mdwn b/lkcl.mdwn
index b0853355ccf1743017793419efa8a45e6b67121e..657c3791d569994153f3c354bfe287f0ec013412 100644 (file)
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -4,22 +4,70 @@ Lead dev and Project Coordinator for Libre-SOC.
 
 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
+* <https://readthedocs.org/profiles/lkcl/> readthedocs link
+* <http://twitter.com/lkcl>
 
 # Status tracking
 
 move things along from one stage to the next
 
+## Priority tasks to keep an eye on
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=195> Power ISA Formal Proof
+  EUR 6550
+* <https://bugs.libre-soc.org/show_bug.cgi?id=198> nmutil/etc Formal Proofs
+   EUR 8650
+* <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
+  EUR 5000
+
 ## Currently working on
 
  - Project Management
- - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix (check if already RFPd)
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
+   - EUR 1500
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
+   - EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
+   - EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
+   - EUR 1000
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
+   - EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
+   - EUR 1000 of 1250 shared
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
+ - https://bugs.libre-soc.org/show_bug.cgi?id=575
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
+   - EUR 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
- - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
- - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
- - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
@@ -28,7 +76,7 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
    - EUR 50, shared with samuel 10%
  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
+
  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
    - EUR 50, shared with samuel (EUR 350)
@@ -36,26 +84,118 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
- - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
-   - EUR 400 shared 25% [[mnolan]] EUR 100
- - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
-   - EUR 500 shared [[mnolan]] samuel, TBD split
- - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
    - EUR 200
- - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
-   - EUR 250 (share with cole)
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
+   - donated
+   - parent #198
+   - EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
+  - MultiCompUnit (and Function Units) proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
+  - donated
+  - parent #195
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation 
+
+## Completed but not yet submitted:
+
+TO SORT
+
+28feb2022
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
+   * EUR 1500 (shared with [[tplaten]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
+   * EUR 1500 (shared with [[tplaten]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
+   * EUR 1000 (shared with [[tplaten]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
+   * EUR 500 (shared with [[programmerjake]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
+   * EUR 400 (shared with [[programmerjake]])
+
+before that
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
+   - EUR 1600
+   - EUR 800 shared with [[klehman]]
+   - EUR 800 shared with [[lkcl]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
+   - EUR 800
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
+   - EUR 500
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
- - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
- - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API 
 
-## Completed but not yet submitted:
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
+   - EUR 150
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
+   - EUR 200
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
+   - EUR 150
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
+   - EUR 200
+   - donated
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
+   - EUR 700
+   - (lip6.fr donated)
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
+   - (total EUR 400 25% donated by LIP6)
+   - EUR 100 lkcl
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
+   - EUR 900
+   - shared with [[lxo]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
+   - EUR 1100
+   - shared with lauri, jacob
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
+   - EUR 1250
+   - Shared 50% with Staf
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
+   - EUR 300
+   - Shared with Staf, cole
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
+   - EUR 450
+   - Shared with Staf
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
+   - Project 2019-10-043 06dec2020 wishbone
+   - EUR (TBD)
+
+### Project 2019-10-029 14mar2020 coriolis2
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
+   - (total EUR 100 shared 50% with staf)
+   - EUR 50 lkcl
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
+   - (total EUR 1500 shared 50% with LIP6)
+   - EUR 750 lkcl
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
+   - (total EUR 400 shared 75% with LIP6)
+   - EUR 300 lkcl
+
+### Project 2019-02-012 06dec2020 Core
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
+   - EUR 750 donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
+   - EUR 1500
+
+### Project 2019-10-043 06dec2020 wishbone
+
  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
@@ -72,35 +212,55 @@ move things along from one stage to the next
    - EUR 450
  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
    - EUR 100
- - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
-
-donated:
-
  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
-     - with [[lkcl]]
- - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
- - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
-     - functions needed for simulator
-     - Shared 90% with [[lkcl]]
- - <https://bugs.libre-soc.org/show_bug.cgi?id=211> parent #198
-     - Formal proof of decoder
-     - EUR 200
- - <https://bugs.libre-soc.org/show_bug.cgi?id=306> parent #195
-     - POWER9 ALU proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=332> parent #195
-     - POWER9 CR proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=335> parent #195
-     - POWER9 BRANCH proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=331> parent #195
-     - POWER9 LOGICAL proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=340> parent #195
-    - POWER9 ROTATE proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
-    - MultiCompUnit (and Function Units) proof
+   - EUR 200 donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
+   - EUR 250 (share with cole)
+
+### Project 2019-10-032 06dec2020 proofs
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
+   - parent #195
+   - EUR 400 donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
+   - parent #195
+   - EUR 300 donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
+   - EUR 400 donated
+   - parent #195
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
+   - EUR 400 donated
+   - parent #195
 
 ## Submitted for NLNet RFP
 
-submitted but not confirmed paid:
+submitted 2021-dec-09 but not confirmed paid
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
+   - EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
+   - EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
+   - EUR 800 shared between:
+   - EUR 500 [[lkcl]]
+   - EUR 300 [[tplaten]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
+   - EUR 5500 shared between:
+   - EUR 3850 lkcl
+   - EUR 1650 Others
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
+   - EUR 1600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
+   - EUR 600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
+   - EUR 500 shared between:
+   - EUR 100 [[lkcl]]
+   - EUR 325 dmitry
+   - EUR 75 maciej
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
+
 
 ### Project 2019-02-012 04sep2020 Core
 
@@ -113,6 +273,12 @@ submitted but not confirmed paid:
 
 donation from NLNet confirmed received:
 
+### coriolis2 2021-apr-04
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
+   - EUR 3000
+   - shared with Staf 50%
+
 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER 
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
@@ -122,7 +288,7 @@ donation from NLNet confirmed received:
     - EUR 250, functions needed for simulator
     - Shared 20% with [[mnolan]], EUR 50
 
-#### proofs 2019-10-032
+### proofs 2019-10-032
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
    - EUR 500 shared 20% samuel, EUR 100
@@ -199,7 +365,8 @@ donation from NLNet confirmed received:
 
 ### Project 2019-10-029 Date 14mar2020
 
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
+  - EUR 1200
 
 ### Project 2019-02-012 Date 12mar2020
 
http://libre-riscv.org ikiwiki