sync_up: Add meeting notes page for next week.

[libreriscv.git] / nlnet_2019_standards.mdwn

diff --git a/nlnet_2019_standards.mdwn b/nlnet_2019_standards.mdwn
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--- a/nlnet_2019_standards.mdwn
+++ b/nlnet_2019_standards.mdwn
@@ -1,4 +1,7 @@
-# NL.net proposal
+# NL.net proposal - 2019-10-046
+
+* NLNet Project Page <https://nlnet.nl/project/LibreSoC-Standards/>
+* Top Level bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=174>
 
 ## Project name
 
@@ -125,3 +128,17 @@ all picked up the story.  The list is updated and maintained here:
 * <https://libre-riscv.org/ztrans_proposal/>
 * <https://libre-riscv.org/zfpacc_proposal/>
 * Several other sub-proposals as part of the above.
+
+# Management Summary
+
+The Libre SoC was first funded from NLNet in 2018.  This was for the core
+of the project, based on an informally-developed Hybrid CPU-GPU 3D
+instruction set that had been written (and implemented in a simulator)
+in the 18 months prior to contacting NLNet.  During the implementation
+it became clear that a lot more work would be needed, and, further, that
+to meet proper transparency criteria, the proposed instruction set
+enhancements would need to be properly written up.  In addition,
+negotiations and communications with the Standards Body responsible
+for POWER ISA (the OpenPower Foundation) also needed to be taken into
+consideration.  Therefore this proposal was submitted so that full
+transparency and understanding of the Libre SoC is achieved.