add cesar

[libreriscv.git] / nlnet_2019_wishbone_streaming.mdwn

diff --git a/nlnet_2019_wishbone_streaming.mdwn b/nlnet_2019_wishbone_streaming.mdwn
index 706f2dc566939647d731debeab1686232ed772dc..e40168977de3de352d77aad63b00cbe4a4b13d86 100644 (file)
--- a/nlnet_2019_wishbone_streaming.mdwn
+++ b/nlnet_2019_wishbone_streaming.mdwn
@@ -1,5 +1,9 @@
 # NL.net proposal
 
+* NLNet Project Page <https://nlnet.nl/project/WishboneStreaming/>
+* 2019-10-043
+* Top Level bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=175>
+
 ## Project name
 
 The Libre RISC-V SoC, Wishbone Streaming Proposal
@@ -106,7 +110,8 @@ Dan Gisselquist in SystemVerilog, but none are written in nmigen.
 
 This is a straightforward project. However the timing issues involved
 with Bus Negotiation can be awkward to get right and may need formal
-proofs to properly verify.
+proofs to properly verify.  Dan Gisselquist's work in his area shows
+how it can be done.
 
 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes