re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / nlnet_2021_3mdeb_cavatools.mdwn

diff --git a/nlnet_2021_3mdeb_cavatools.mdwn b/nlnet_2021_3mdeb_cavatools.mdwn
index 6afe255c9b82bb2a3f46c261f4eb1792e4f90140..0acdb183cfa747cce2900c29e4fc88a1dd8ad8cf 100644 (file)
--- a/nlnet_2021_3mdeb_cavatools.mdwn
+++ b/nlnet_2021_3mdeb_cavatools.mdwn
@@ -1,3 +1,7 @@
+# NLnet User-operated Grant Request for 3mdeb Power ISA Simulator
+
+* 2021-08-071
+
 ## Project name
 
 Libre-SOC 3mdeb Cavatools: Power ISA Simulator