+# NLnet User-operated Grant Request for 3mdeb Power ISA Simulator
+
+* 2021-08-071
+* [[nlnet_2021_3mdeb_cavatools/discussion]]
+* <https://bugs.libre-soc.org/show_bug.cgi?id=939>
+
## Project name
Libre-SOC 3mdeb Cavatools: Power ISA Simulator
## Abstract: Can you explain the whole project and its expected outcome(s).
-
+Cavatools is currently a high performance user-operated simulator of
+the RISC-V ISA. The primary objective of the project is to extend it to
+implement the scalar Power ISA and the Libre-SOC Draft SVP64
+Extensions. This will allow rapid prototyping of Extensions to the
+Power ISA long before they reach silicon (which is very costly).
+In turn this helps Libre-SOC to deliver on its commitment to provide
+user-trustable processors for use in Internet routers, desktop,
+smartphone and other user-operated devices where security and transparency
+is expected.
# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
-
+3mdeb is currently helping Libre-SOC with the (horribly slow,
+easy-to-read, easy-to-use) Libre-SOC Power ISA Simulator which is 20,000 times
+slower than cavatools. 3mdeb is also helping with ISA level unit tests in
+Libre-SOC's code base that will be used to cross-validate a huge range of
+Power ISA simulators and actual silicon implementations.
# Requested Amount
# Explain what the requested budget will be used for?
-# Does the project have other funding sources, both past and present?
+* To create a compiler which takes Libre-SOC Machine-readable
+ Power ISA specification files and generate c code
+* To extend cavatools to include support for the Scalar
+ parts of the Power ISA
+* To then add support for Libre-SOC's Draft SVP64 Extensions
+* To enhance it to include gdb "remote" machine interface
+ support
+* To add Power ISA RADIX MMU emulation
+* To extend cavatools to run a very basic linux
+ initramfs in-memory with basic serial console access
+* To demonstrate running first a single core linux kernel
+ and later a SMP one, with busybox
+* To use the exact same Specification c compiler to create
+ an "illegal instruction trap" emulator, integrated
+ into the linux kernel, for emulating Power ISA SIMD instructions
+ (extending the existing trap-and-emulate code already present
+ in ppc64 linux kernel source code)
+# Does the project have other funding sources, both past and present?
+Although there is NLnet funding for the Libre-SOC Simulator
+(written in python) and associayed unit tests, cavatools, which is
+written in c by Peter Hsu, does not have funding for the Power ISA
+aditions. cavatools itself is a very new project.
# Compare your own project with existing or historical efforts.
+Although there are quite a few Power ISA simulators, none of them
+are up-to-date or are suited to high performance, like cavatools.
+cavatools is multi-process and extremely fast, using relatively little
+memory, where power-gem5, which has a different focus and has huge flexibility
+and usefulness for research, uses vast amounts
+of memory and is much slower. cavatools also has hardware-level cycle-accurate emulation which is extremely useful and important for analysing experimental
+instructions, which is a feature that no other Power ISA Simulator has.
+DolphinPC and pearpc are over 15 years old and were targetted at 32 bit
+emulation of much older Power ISA processors. Libre-SOC's python-based
+simulator only achieves aroubd 2,000 instructions per second on
+high performance hardware whereas
+cavatools achieves 200,000 instructions per second per processor
+on modest hardware.
+IBM's own Power ISA simulator is proprietary and, because it contains
+confidential experimentation internal to IBM, may not be made public.
+
## What are significant technical challenges you expect to solve during the project, if any?
+This is at its heart a compiler project, which can be a challenging
+area. However the language being implemented is quite small and limited,
+so the project is relatively straightforward.
## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
+The project will be developed entirely publicly and transparently,
+using Libre-SOC Project Resources which are already set up for trustable
+auditability and transparency. The mailing lists therefore are always
+publicly available.
+
+Online conferences and talks will be given as progress
+is made, as well as working with Libre-SOC to send out development
+reports and progress.
+
# Extra info to be submitted
projects / libreriscv.git / blobdiff