add important clarification of #1033

[libreriscv.git] / nlnet_2022_ongoing / discussion.mdwn

diff --git a/nlnet_2022_ongoing/discussion.mdwn b/nlnet_2022_ongoing/discussion.mdwn
index dda5edc4e5667d0ba2808dc1498a37fb5fe1e503..51c4c07a420e56d783b6e480db9f01a90ded31b1 100644 (file)
--- a/nlnet_2022_ongoing/discussion.mdwn
+++ b/nlnet_2022_ongoing/discussion.mdwn
@@ -42,6 +42,11 @@ Cesar likely do the former, Jacob could do the latter.
 ### Bug 1033
 
 * Create the framework for testing (or choose existing)
+  (jacob: important clarification -- afaict this task is adding new `StateRunner`
+  and `State` subclasses for FPGA/verilator/etc.
+  This task is *not* for creating a new framework or choosing an existing framework,
+  we already have one with implementations for pypowersim, nmigen simulation of the
+  libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
 * Add specialisation for pypowersim, microwatt (verilator), FPGA.
 * Cavatools out of scope.
 * Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?