# NL.net proposal
+* 2022-08-051, approved 24 Oct 2022
+* [[nlnet_2022_opf_isa_wg/discussion]]
+* <https://bugs.libre-soc.org/show_bug.cgi?id=952>
## Project name
-OpenPOWER ISA RFCs
+Libre-SOC OpenPOWER ISA RFCs
## Website / wiki
<https://libre-soc.org/nlnet_2022_opf_isa_wg>
+## NLnet Funding approved 25-Oct-2022 under EU Grant 101069594
+
+This project is funded through the [NGI Zero Entrust Fund](https://nlnet.nl/entrust), a fund established by [NLnet](https://nlnet.nl) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) program. Learn more on the [NLnet project page](https://nlnet.nl/project/Libre-SOC-OpenPOWER-ISA#ack).
+
+
+[<img src="https://nlnet.nl/logo/banner.png" alt="NLnet foundation logo" width="20%" />](https://nlnet.nl)
+[<img src="https://nlnet.nl/image/logos/NGI0Entrust_tag.svg" alt="NGI Zero Entrust Logo" width="20%" />](https://nlnet.nl/entrust)
+
+# Summary
+
+In earlier NLnet Grants, thanks to EU funding, we developed Draft
+SVP64 (a Vector Extension for the Power ISA), around a hundred
+new Draft instructions that dramatically improves the Supercomputing-class
+Power ISA, a Simulator, thousands
+of unit tests and over 350 pages of documentation. What we could
+not do however was submit a Specification to the OpenPOWER ISA
+Working Group because the ISA WG was in the process of being
+ratified. That has now been done, and we need to begin the
+formal process of writing up "Requests For Change" and submitting
+them. The end result will be an extremely powerful Vector ISA suitable
+for use in Digitally-Sovereign end-user products.
+
+# Submission to NLnet
+
Please be short and to the point in your answers; focus primarily on
the what and how, not so much on the why. Add longer descriptions as
attachments (see below). If English isn't your first language, don't
The current NLnet funding to date has allowed Libre-SOC to develop
one of the most powerful Scalable Vector ISAs in the world.
The 25-year-old Power ISA, developed and curated by IBM, was
-transferred to the OpenPOWER Foundation, and is the basis of
+transferred to the OpenPOWER Foundation, and is the basis on
+which, with NLnet EU funding, we have based
Simple-V, the Draft Scalable Vector Extension.
Simple-V *needs* to be submitted to the OPF ISA Working Group,
https://ftp.libre-soc.org/simple_v_spec.pdf
However the
-process of submitting Requests For Change, at the time of writing,
+process of submitting RFCs (Requests For Change), at the time of writing,
still has not been publicly announced and opened up. We expect it
-to be very soon, but obviously could not begin any RFC Submission as
-part of the earlier NLnet funding.
+to be very soon, but obviously could not begin any RFC Submission
+as part of earlier NLnet funding. The timing is now right.
-We will also become informed very shortly of the procedures but anticipate
+We will become publicly informed very shortly of the procedures but anticipate
it to include development and submission of Compliance Test Suites
(already partly covered by Simple-V unit tests, kindly funded by NLnet)
as well as ongoing work on the Simulator.
# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
A lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
-and includes the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
-the world's first in-place Discrete Cosine Transform algorithm;
-Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs) to do an 800,000 transistor fully automated RTL2GDSII
-tape-out; the side-benefits alone are enormous.
+and includes
+
+* the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
+* the world's first in-place Discrete Cosine Transform algorithm;
+* Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
+ to do an 800,000 transistor fully automated RTL2GDSII
+tape-out;
+* development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
+ ASIC ever taped-out in Europe (and funded by Horizon 2020)
+* development of an Interoperability "Test API" for Power ISA systems,
+ with thousands of unit tests.
+
+and much more. The side-benefits alone for EU citizens are enormous.
# Requested Amount
# Explain what the requested budget will be used for?
+Time and resource, primarily manpower, to prepare and submit the documentation
+to OPF. To give us legal compliance for the development
+work carried out over the past four years, as part of the
+transfer to the OpenPOWER Foundation.
+
* ongoing communication with the OpenPOWER Foundation ISA Working Group
* preparation of a large number of RFCs (380 pages total so far) through
the External RFC Process
We are developing a Cray-style Scalable Vector ISA Extension for
the Supercomputing-class Power ISA. Similar historic ISAs include
-Cray YMP1, ETA-19, Cyber CDC 205. More recent is the NEC SX Aurora.
+Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
They are all proprietary systems: Libre-SOC's efforts are entirely
FOSSHW.
Open Scalable Vector ISAs include MRISC32/64 (in early development) and
RISC-V RVV. Advocates of RISC-V have been discovering to their dismay
-that RVV and RISC-V has fundamental issues that cannot be fixed.
-Additionally, submission of ISA modifications requires RISCV Foundation
+that RVV and RISC-V ISA has fundamental design issues that cannot be fixed.
+Additionally, submission of RISCV ISA modifications requires RISCV Foundation
Membership which puts us under impossible conflict of interest with
Full Transparency Conditions not only with NLnet but also with
EU Auditing Requirements. By direct contrast OPF External RFC Submission
## What are significant technical challenges you expect to solve during the project, if any?
-
+The main challenge is one of communication. The majority of the technical
+development has been done thanks to NLnet
+but it was so complex and comprehensive that it risks overwhelming the ISA
+WG Members, whose primary driver has of course been IBM for the past 25
+years.
+
+Libre-SOC proposes taking the Power ISA into mainstream computing,
+including Video Decode, 3D, GPU workloads, cryptography, and Desktop
+and Portable devices, all of which are far different from IBM's traditional
+Mainframe-style multi-billion-dollar Supercomputing business.
+We therefore have to be both deeply respectful of their achievements, and
+non-disruptive to their customer base, but
+also appropriately assertive now that the ISA is managed by the OpenPOWER
+Foundation.
## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
+Partly covered above, Libre-SOC is exclusively FOSSHW and full transparency
+is paramount. That said we recognise that no FOSSHW team is going to
+manufacture FOSS ASICs in 7nm (unless several billion dollars is available
+to buy a Foundry and open up its PDK). To that end RED Semiconductor Ltd
+has been formed by us as an Independent Entity,
+which will commercialise Libre-SOC's designs and handle
+any Commercially-confidential matters that a Transparency-committed
+FOSSHW team simply
+cannot. Thus, RS will join the OpenPOWER Foundation and help ensure,
+from the "other side of the fence", that matters progress smoothly
+for IBM and other OPF Members.
+
+RED Semiconductor Ltd will the commercial point of contact for Simple-V
+where Organisations are unable to deal with FOSS Entities. This maximises
+the broad market benefit of the technology, in line with European Objectives.
+
+We are already set to submit presentations through multiple Conferences
+as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
+OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
+so is accessible to all.
# Extra info to be submitted
-* TODO URLs etc
+the budget is high because we honestly do not know yet how much work
+IBM and the ISA WG expects us to do. we do however know that there
+will be announcements very soon. If it turns out to be less work
+we are more than happy to go with a proportionately smaller budget.
projects / libreriscv.git / blobdiff