-# NLnet SVP64 ISA Expansion Project Grant
+# NLnet Simple-V ISA Expansion Project Grant
-* Code: 2023-12-XXX
-* Submitted: XX Dec 2023
+* Code: 2023-12-059
+* Submitted: 24 Nov 2023
* Toplevel bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=1211>
This project is applying for funding through the [NGI Zero Core Fund](https://nlnet.nl/core), a fund established by [NLnet](https://nlnet.nl) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) programme under grant agreement No 101092990.
## Project name
-SVP64 ISA Expansion Project
+Simple-V ISA Expansion Project
## Website / wiki
-<https://libre-soc.org/nlnet_2023_svp64_riscv>
+<https://libre-soc.org/nlnet_2023_simplev_riscv>
Please be short and to the point in your answers; focus primarily on
the what and how, not so much on the why. Add longer descriptions as
## Abstract: Can you explain the whole project and its expected outcome(s).
-This project, a collaboration between RED Semiconductor and LibreSOC, will build on work already completed in bringing Simple-V/SVP64 ISA-agnostic vectorised microprocessor architecture to the RISC-V community, giving access to an open-source ISA who's performance competes with high-end incumbents like ARM, Intel and IBM. Bringing open-source High Performance Computing to all developers, will fuel the next wave of innovation. The outcome of the project will be the validation of Simple-V/SVP64 architecture on RISC-V base architecture, demonstrated in a software simulator.
+This project will build on work already completed to refresh and update the Simple-V ISA-agnostic Vector architecture for the RISC-V community, creating an open-source ISA whose performance matches with high-end incumbents like ARM, Intel and IBM. Bringing open-source High Performance Computing to all developers will fuel the next wave of innovation. The outcome of the project will be the validation of an updated Simple-V architecture on RISC-V, demonstrated in two software simulators (ISACaller and sv-spike).
-RISC-V is the largest open-source global community for microprocessor architecture enabling developers to create custom instructions to solve computational challenges, and develop their own SoC hardware implementations. Simple-V/SVP64 extensions will deliver accelerated CPU performance for rapidly growing demands at the Edge for data processing, autonomy and cryptography, driven by global megatrends like AI, metaverse and social media, as well as social issues like healthcare and critical infrastructure. This project enables the developer community to access the benefits of Simple-V/SVP64 code efficiency on RISC-V.
+RISC-V is the largest open-source global community for microprocessor architecture enabling developers to create custom instructions to solve computational challenges, and develop their own SoC hardware implementations. Simple-V extensions will deliver accelerated CPU performance for rapidly growing demands at the Edge for data processing, autonomy and cryptography, driven by global megatrends like AI, metaverse and social media, as well as social issues like healthcare and critical infrastructure. This project enables the developer community to access the benefits of Simple-V code efficiency on RISC-V.
# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
-A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings from previous projects to create a powerful RISC-V based vector ISA capable of the performance of POWER. A full project list is maintained at: <https://libre-soc.org/nlnet_proposals/>
+A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings and work from previous projects to update RISC-V to a powerful vector ISA capable of the performance of the Power ISA. A full project list is maintained at: <https://libre-soc.org/nlnet_proposals/>
they include recently:
* <https://libre-soc.org/nlnet_2022_opf_isa_wg/> - improving SVP64
# Explain what the requested budget will be used for?
-
Key phases of this project are:
-* Assessment of the missing RISC-V instructions (RISC-V RV64GC is only 96 instructions whereas POWER ISA SFFS is 214) which are present in Power ISA 3.0 and required to enable comparable performance from RISC-V with Simple-V/SVP64
-
+* Assessment of the missing RISC-V instructions (RISC-V RV64GC is only 96 instructions
+ whereas POWER ISA SFFS is 214) which are present in Power ISA 3.0 and required to
+ enable comparable performance from RISC-V with Simple-V
* Implementation of the missing RISC-V instructions and instruction forms that makes is comparable with POWER ISA in the Scalar ISA space.
-
-* Assessment of application of Simple-V Vector Prefixing to SVP64, building on the work already done under NLnet Grant 2019-10-012 <https://libre-soc.org/nlnet_2018/>
-
+* Assessment of application of Simple-V Vector Prefixing, building on the work already
+ done under NLnet Grant 2019-10-012 <https://libre-soc.org/nlnet_2018/>
* Implementation of Simple-V in the Libre-SOC Simulator, ISACaller.
-
-* Definition of assembler and disassembler for RISC-V instructions and also SVP64 in the Libre-SOC infrastructure.
-
-* Upgrading (with the newly created instructions and forms) sv-spike assembler development which was prototyped previously for Simple-V Specification:
+* Definition of assembler and disassembler for RISC-V instructions and also Simple-V
+ in the Libre-SOC infrastructure.
+* Upgrading (with the newly created instructions and forms) sv-spike assembler
+ development which was prototyped previously for Simple-V Specification:
<https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv>
-
-* Adding a comprehensive unit test base for the new instructions which can then be tested against sv-spike as well as ISACaller. Conversion of previously created instructions to the new format used in Libre-SOC, and adding the newly defined and created instructions.
+* Adding a comprehensive unit test base for the new instructions which can then be
+ tested against sv-spike as well as ISACaller. Conversion of previously created
+ instructions to the new format used in Libre-SOC, and adding the newly defined
+ and created instructions.
<https://git.libre-soc.org/?p=riscv-tests.git;a=shortlog;h=refs/heads/sv>
-
-* Documentation, demonstrations and Conference Papers. This will include porting results of other completed projects (cryptoprimitives, video) from POWER ISA to the RISC-V/Simple-V/SVP64 environment
-
-* Research and assessment of ARM7 and i486 (both on opencores.org)as to their feasibility for applying Simple-V Prefixing in future development projects
-
-By far the largest element of the budget is attributed to labour costs of the team involved from RED Semiconductor and LibreSOC - the project is entirely software-based and no additional hardware requirements are anticipated. A small budget of €5k is allocated to travel for presentation of the project results at industry conferences.
+* Documentation, demonstrations and Conference Papers. This will include porting
+ results of other completed projects (cryptoprimitives, video) from POWER ISA to
+ the RISC-V/Simple-V environment
+* Research and assessment of ARM7 and i486 (both on opencores.org) as well as ARC
+ as to their feasibility for applying Simple-V Prefixing in future development projects
+* Development and publication of paper in Academic Journals and presentation
# Does the project have other funding sources, both past and present?
# Compare your own project with existing or historical efforts.
+Other modern ISAs claiming to be Vectors are in fact Packed or Predicated SIMD.
+True Cray-style Vector ISAs do not have Vertical-First or Data-Dependent
+Fail-First because these are entirely novel Computer Science concepts
+(developnet of which entirely funded by NLnet, with gratitude).
+Bottom line there are zero comparable projects but the project has learned
+significantly from past ISAs dating back as far as the early 1960s.
+
## What are significant technical challenges you expect to solve during the project, if any?
-The key technical challenge in this project is the creation of special SVP64 instructions that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community.
+The key technical challenge in this project is to rework the special Simple-V
+instructions (from the early iteration of four years ago) that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community.
Based on the previous work of Vectorising RISC-V and POWER using Simple-V already, this project is well within the scope of the experienced teams at LibreSOC and RED Semiconductor, but is extremely detailed and comprehensive, requiring meticulous attention to detail and a very high standard of Project Management. This is a sustained standard and practices developed already over a five year period that will continue to be rigorously applied.
## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
-The Libre-SoC has a full set of resources for Libre Project Management and development: mailing list, bugtracker, git repository, wiki and also will be doing linkedin posts in other outreach - all listed here: https://libre-soc.org/
-
-
+Libre-SoC has a full set of resources for Libre Project Management and development: mailing list, bugtracker, git repository, wiki and also will be doing linkedin posts and other outreach as well as Academic-quality papers - all listed here: <https://libre-soc.org/>
# Extra info to be submitted
+This grant is associated with the binutils grant
+<https://libre-soc.org/nlnet_2023_simplev_riscv_binutils>
+
# Questions Received date: TODO
projects / libreriscv.git / blobdiff