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[libreriscv.git] / nlnet_2023_simplev_riscv_binutils.mdwn

diff --git a/nlnet_2023_simplev_riscv_binutils.mdwn b/nlnet_2023_simplev_riscv_binutils.mdwn
index 2fe58b93d2d3f11b0ca3a2d6e1f262b58a5f1c23..1f4b3c47b0d3fb5d6a88224234bb962a48e227be 100644 (file)
--- a/nlnet_2023_simplev_riscv_binutils.mdwn
+++ b/nlnet_2023_simplev_riscv_binutils.mdwn
@@ -1,8 +1,8 @@
-# NLnet Binutils for Simple-V ISA Expansion Project Grant
+# Binutils with Simple-V ISA Expansion Project
 
-Code: 2023-12-XXX
+Code: 2023-12-121
 
-Submitted: XX Dec 2023
+Submitted: 30 nov 2023
 
 Toplevel bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=1212>
 
@@ -10,7 +10,7 @@ This project is applying for funding through the NGI Zero Core Fund, a fund esta
 
 ## Project name
 
-Binutils for Simple-V ISA Expansion Project
+Binutils with Simple-V ISA Expansion Project
 
 ## Website / wiki
 
@@ -20,7 +20,8 @@ Please be short and to the point in your answers; focus primarily on the what an
 
 ## Abstract: Can you explain the whole project and its expected outcome(s).
 
-This project is to enhance binutils tools to continue the autogenerated supportfor the
+This project is to enhance binutils tools to continue the autogenerated support
+for the
 RISC-V, Power and other ISAs, and to also support Simple-V Vectorisation capabilities.
 It will directly support the ISA Expansion project
 <https://libre-soc.org/nlnet_2023_simplev_riscv>
@@ -51,7 +52,7 @@ Key phases of this project are:
   and SVP64/Power (currently based on an early iteration of libopid)
 * Definition of assembler and disassembler for RISC-V
   instructions and also SVP32, 48 and 64 Vector Prefixing formats, using libopid
-* Completion of definitions of Simple-V/Single formats SVP64Single, SVP48Singe and SVP32Single
+* Completion of definitions of Simple-V/Single formats SVP64Single, SVP48Single and SVP32Single
   and implementation support of the same for both Power and RISC-V
   (https://libre-soc.org/openpower/sv/svp64-single/)
 * Test vectors for libopid and binutils
@@ -72,13 +73,13 @@ and source code.
 
 ##What are significant technical challenges you expect to solve during the project, if any?
 
-The key technical challenge in this project is the creation of the binutil tool set that enables developers to take advantage of the Simple-V/SVP64 extensions and capabilities for RISC-V, and to successfully develop and debug complex code. The binutil tools will be comprehensively tested and verified with the newly developed instructions (developed within the separate project) in order to lead the way for its use in the widespread developer community.
+The key technical challenge in this project is the creation of the binutils tool set that enables developers to take advantage of the Simple-V/SVP64 extensions and capabilities for RISC-V, and to successfully develop and debug complex code. binutils will be comprehensively tested and verified with the newly developed instructions (developed within the separate project) in order to lead the way for its use in the widespread developer community.
 
-This project relies on the experience and expertise of a subset of the RED Semiconductor/LibreSOC team who have developed similar tools for use with other ISAs.
+This project relies on the experience and expertise of the LibreSOC team who have developed similar tools for use with other ISAs.
 
 ##Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 
-The Libre-SoC has a full set of resources for Libre Project Management and development: mailing list, bugtracker, git repository, wiki and also will be doing linkedin posts in other outreach - all listed here: <https://libre-soc.org/>
+Libre-SOC has a full set of resources for Libre Project Management and development: mailing list, bugtracker, git repository, wiki and also will be doing linkedin posts in other outreach - all listed here: <https://libre-soc.org/>
 
 #Extra info to be submitted