-# NLnet Binutils for SVP64 ISA Expansion Project Grant
+# Binutils with Simple-V ISA Expansion Project
Code: 2023-12-XXX
Submitted: XX Dec 2023
-Toplevel bugreport: https://bugs.libre-soc.org/
+Toplevel bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=1212>
This project is applying for funding through the NGI Zero Core Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme under grant agreement No 101092990.
## Project name
-Binutils for SVP64 ISA Expansion Project
+
+Binutils with Simple-V ISA Expansion Project
## Website / wiki
-https://libre-soc.org/nlnet_2023_svp64_riscv
+
+<https://libre-soc.org/nlnet_2023_simplev_riscv_binutils>
Please be short and to the point in your answers; focus primarily on the what and how, not so much on the why. Add longer descriptions as attachments (see below). If English isn't your first language, don't worry - our reviewers don't care about spelling errors, only about great ideas. We apologise for the inconvenience of having to submit in English. On the up side, you can be as technical as you need to be (but you don't have to). Do stay concrete. Use plain text in your reply only, if you need any HTML to make your point please include this as attachment.
## Abstract: Can you explain the whole project and its expected outcome(s).
-This project is a collaboration between RED Semiconductor and LibreSOC to create binutil tools that support the development of Simple-V and SVP64 capabilities for the open-source RISC-V ISA. It will directly support the ISA Expansion project for which a separate grant application has been made, and will build on learnings from binutils developed for POWER ISA. The outcome of the project will be the completion of binutil tools capable of creating and managing binary program files, including handling object files, libraries, profile data, and assembly source code.
+This project is to enhance binutils tools to continue the autogenerated supportfor the
+RISC-V, Power and other ISAs, and to also support Simple-V Vectorisation capabilities.
+It will directly support the ISA Expansion project
+<https://libre-soc.org/nlnet_2023_simplev_riscv>
+for which a separate grant application has been made, and will build on learnings from
+binutils developed for POWER ISA and SVP64/Power. The outcome of the project will be the completion of binutil tools capable of creating and managing binary program files, including handling object files, libraries, profile data, and assembly source code, as well as
+providing a machine-readable database and associated library for other projects to
+manipulate supported Instruction sets.
-The completed tools will be made available to developers via LibreSOC's website and git repositories.
+# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
-#Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
-A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings from previous projects to create a powerful RISC-V based vector ISA capable of the performance of POWER. A full project list is maintained at: https://libre-soc.org/nlnet_proposals/ they include recently:
+A sequence of projects enabled early development (four years ago, 2019-03-012)
+of vectorisation techniques in the RISC-V domain, and later higher performance
+demonstration with OpenPOWER ISA (2022-08-051). A full project list is maintained at: https://libre-soc.org/nlnet_proposals/ they include recently:
* https://libre-soc.org/nlnet_2022_opf_isa_wg/ - improving SVP64 and submitting it to the OpenPOWER ISA Technical Working Group.
-
* https://libre-soc.org/nlnet_2021_crypto_router/ - proving, improving, and demonstrating that SVP64 is capable of handling cryptographic primitives in an extreme power-efficient compact way as the basis for higher security products
-#Requested Amount
-EUR 50,000.
+# Requested Amount
-#Explain what the requested budget will be used for?
-Key phases of this project are:
+EUR 85,000.
-* Definition of assembler and disassembler and other binutil tools for RISC-V instructions and also SVP64 in the Libre-SOC infrastructure.
+# Explain what the requested budget will be used for?
-* Creation of test code routines based on output of previous POWER ISA projects (cryptoprimitives, codecs), and testing and validation of the binutils
+Key phases of this project are:
+* Completion of libopid (an instruction database parser)
+* Completion of libopid porting of Libre-SOC infrastructure both Scalar Power ISA
+ and SVP64/Power (currently based on an early iteration of libopid)
+* Definition of assembler and disassembler for RISC-V
+ instructions and also SVP32, 48 and 64 Vector Prefixing formats, using libopid
+* Completion of definitions of Simple-V/Single formats SVP64Single, SVP48Singe and SVP32Single
+ and implementation support of the same for both Power and RISC-V
+ (https://libre-soc.org/openpower/sv/svp64-single/)
+* Test vectors for libopid and binutils
* Documentation, demonstrations and Conference Papers.
-90% of the budget is attributed to labour costs of the team involved from RED Semiconductor and LibreSOC - the project is entirely software-based and no additional hardware requirements are anticipated. A small budget of €5k is allocated to travel for presentation of the project results at industry conferences.
+# Does the project have other funding sources, both past and present?
-#Does the project have other funding sources, both past and present?
NGI Search, NGI POINTER, and NLnet Grants have been the sole source of funding for this development programme over the past five years, and for the project in this application. Four grants are at stages of completion at the time of writing (two nearing end).
#Compare your own project with existing or historical efforts.
+
+There are a few machine-readable instruction databases around: they tend not to
+be used massively extensively to for example auto-generate c code for use in
+binutils. Most assembler/disasembler instruction parsing oddly is done by hand-editing
+each and every instruction (10,000 in the case of Power ISA). This project is pretty unique
+and includes auto-code-generation so as to avoid transliteration errors between ISA Spec
+and source code.
+
##What are significant technical challenges you expect to solve during the project, if any?
+
The key technical challenge in this project is the creation of the binutil tool set that enables developers to take advantage of the Simple-V/SVP64 extensions and capabilities for RISC-V, and to successfully develop and debug complex code. The binutil tools will be comprehensively tested and verified with the newly developed instructions (developed within the separate project) in order to lead the way for its use in the widespread developer community.
This project relies on the experience and expertise of a subset of the RED Semiconductor/LibreSOC team who have developed similar tools for use with other ISAs.
##Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
-The Libre-SoC has a full set of resources for Libre Project Management and development: mailing list, bugtracker, git repository, wiki and also will be doing linkedin posts in other outreach - all listed here: https://libre-soc.org/
+
+The Libre-SoC has a full set of resources for Libre Project Management and development: mailing list, bugtracker, git repository, wiki and also will be doing linkedin posts in other outreach - all listed here: <https://libre-soc.org/>
#Extra info to be submitted
-#Questions Received date: TODO
+
+This grant is associated with the binutils grant
+<https://libre-soc.org/nlnet_2023_simplev_riscv>
+
+#Questions Received date:
+
+TODO
projects / libreriscv.git / blobdiff