fosdem2024_bigint: remove test.dia

[libreriscv.git] / nlnet_2023_simplev_riscv_binutils.mdwn

diff --git a/nlnet_2023_simplev_riscv_binutils.mdwn b/nlnet_2023_simplev_riscv_binutils.mdwn
index 1187bcf2be1c3e592fe67aea20b349642230096f..df02ae28d6ce8e71fb41be44132ef4cfb66f1308 100644 (file)
--- a/nlnet_2023_simplev_riscv_binutils.mdwn
+++ b/nlnet_2023_simplev_riscv_binutils.mdwn
@@ -1,4 +1,4 @@
-# NLnet Binutils for Simple-V ISA Expansion Project Grant
+# Binutils with Simple-V ISA Expansion Project
 
 Code: 2023-12-XXX
 
@@ -10,7 +10,7 @@ This project is applying for funding through the NGI Zero Core Fund, a fund esta
 
 ## Project name
 
-Binutils for Simple-V ISA Expansion Project
+Binutils with Simple-V ISA Expansion Project
 
 ## Website / wiki
 
@@ -46,19 +46,30 @@ EUR 85,000.
 
 Key phases of this project are:
 
-* Definition of assembler and disassembler and other binutil tools for RISC-V
-  instructions and also SVP32, 48 and 64 in the Libre-SOC infrastructure.
-* Creation of test code routines based on output of previous POWER ISA projects
-  (cryptoprimitives, codecs), and testing and validation of the binutils
+* Completion of libopid (an instruction database parser)
+* Completion of libopid porting of Libre-SOC infrastructure both Scalar Power ISA
+  and SVP64/Power (currently based on an early iteration of libopid)
+* Definition of assembler and disassembler for RISC-V
+  instructions and also SVP32, 48 and 64 Vector Prefixing formats, using libopid
+* Completion of definitions of Simple-V/Single formats SVP64Single, SVP48Singe and SVP32Single
+  and implementation support of the same for both Power and RISC-V
+  (https://libre-soc.org/openpower/sv/svp64-single/)
+* Test vectors for libopid and binutils
 * Documentation, demonstrations and Conference Papers. 
 
-
 # Does the project have other funding sources, both past and present?
 
 NGI Search, NGI POINTER, and NLnet Grants have been the sole source of funding for this development programme over the past five years, and for the project in this application. Four grants are at stages of completion at the time of writing (two nearing end).
 
 #Compare your own project with existing or historical efforts.
 
+There are a few machine-readable instruction databases around: they tend not to
+be used massively extensively to for example auto-generate c code for use in
+binutils. Most assembler/disasembler instruction parsing oddly is done by hand-editing
+each and every instruction (10,000 in the case of Power ISA). This project is pretty unique
+and includes auto-code-generation so as to avoid transliteration errors between ISA Spec
+and source code.
+
 ##What are significant technical challenges you expect to solve during the project, if any?
 
 The key technical challenge in this project is the creation of the binutil tool set that enables developers to take advantage of the Simple-V/SVP64 extensions and capabilities for RISC-V, and to successfully develop and debug complex code. The binutil tools will be comprehensively tested and verified with the newly developed instructions (developed within the separate project) in order to lead the way for its use in the widespread developer community.