re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / nlnet_proposals.mdwn

diff --git a/nlnet_proposals.mdwn b/nlnet_proposals.mdwn
index b5a4c8c60644c335526a749aeaedfa63684122b8..8f1447dd19ab94c78d8942c09ca5a591f5c7a96e 100644 (file)
--- a/nlnet_proposals.mdwn
+++ b/nlnet_proposals.mdwn
@@ -1,7 +1,6 @@
 # NLNet Proposals
 
 * Idea: robotics proposal (TBD, jacky)
-* [[nlnet_2021_crypto_router]] - 12jan2021 draft - submitter found (jan) submitted 24jan2021
 
 ## accepted
 
@@ -14,6 +13,9 @@
 * [[nlnet_2019_wishbone_streaming]] - submitted 2019sep26 - submitter found (hank)  - accepted 20dec2019, MOU done
 * [[nlnet_2019_standards]] - submitted 2019sep27 - submitter found (phcomp)  - accepted 20dec2019, MOU done
 * Additional related proposal from Chips4Makers - submitter found (chips4makers) - accepted 20dec2019
+* [[nlnet_2021_crypto_router]] - 12jan2021 draft - submitter found (jan) submitted 24jan2021
+* [[nlnet_2021_lip6_vlsi]] LIP6 VLSI tools - submitted 29jul2021 - Ref 2021-08-049 - accepted 09nov2021
+* [[nlnet_2021_3mdeb_cavatools]] 3mdeb Power ISA Simulator - submitted 31jul2021 - Ref 2021-08-071 - accepted 09nov2021
 
 ## not accepted / withdrawn