build,vendor: never carry around parts of differential signals.

[nmigen.git] / nmigen / vendor / lattice_ecp5.py

diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py
index cd2f7202a80cea92af3ceba0787b71701684ce96..cd5c99acf2010cb7f9254aed988692e1ce798d6d 100644 (file)
--- a/nmigen/vendor/lattice_ecp5.py
+++ b/nmigen/vendor/lattice_ecp5.py
@@ -553,9 +553,9 @@ class LatticeECP5Platform(TemplatedPlatform):
                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
-        for bit in range(len(port)):
+        for bit in range(pin.width):
             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
-                i_I=port[bit],
+                i_I=port.io[bit],
                 o_O=i[bit]
             )
         return m
@@ -565,10 +565,10 @@ class LatticeECP5Platform(TemplatedPlatform):
                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
-        for bit in range(len(port)):
+        for bit in range(pin.width):
             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
                 i_I=o[bit],
-                o_O=port[bit]
+                o_O=port.io[bit]
             )
         return m
 
@@ -577,11 +577,11 @@ class LatticeECP5Platform(TemplatedPlatform):
                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
-        for bit in range(len(port)):
+        for bit in range(pin.width):
             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
                 i_T=t,
                 i_I=o[bit],
-                o_O=port[bit]
+                o_O=port.io[bit]
             )
         return m
 
@@ -590,63 +590,63 @@ class LatticeECP5Platform(TemplatedPlatform):
                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
-        for bit in range(len(port)):
+        for bit in range(pin.width):
             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],
-                io_B=port[bit]
+                io_B=port.io[bit]
             )
         return m
 
-    def get_diff_input(self, pin, p_port, n_port, attrs, invert):
+    def get_diff_input(self, pin, port, attrs, invert):
         self._check_feature("differential input", pin, attrs,
                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
-        for bit in range(len(p_port)):
+        for bit in range(pin.width):
             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
-                i_I=p_port[bit],
+                i_I=port.p[bit],
                 o_O=i[bit]
             )
         return m
 
-    def get_diff_output(self, pin, p_port, n_port, attrs, invert):
+    def get_diff_output(self, pin, port, attrs, invert):
         self._check_feature("differential output", pin, attrs,
                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
-        for bit in range(len(p_port)):
+        for bit in range(pin.width):
             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
                 i_I=o[bit],
-                o_O=p_port[bit],
+                o_O=port.p[bit],
             )
         return m
 
-    def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
+    def get_diff_tristate(self, pin, port, attrs, invert):
         self._check_feature("differential tristate", pin, attrs,
                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
-        for bit in range(len(p_port)):
+        for bit in range(pin.width):
             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
                 i_T=t,
                 i_I=o[bit],
-                o_O=p_port[bit],
+                o_O=port.p[bit],
             )
         return m
 
-    def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
+    def get_diff_input_output(self, pin, port, attrs, invert):
         self._check_feature("differential input/output", pin, attrs,
                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
-        for bit in range(len(p_port)):
+        for bit in range(pin.width):
             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],
-                io_B=p_port[bit],
+                io_B=port.p[bit],
             )
         return m