expand SVi to 8 bits

[libreriscv.git] / openpower / isa / simplev.mdwn

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index cada3b6ae0066c465ca360cab66476396d978ef3..d283db9661bfd0776e2dbdcef046f09fe61050ab 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -10,13 +10,13 @@ Pseudo-code:
     VLimm <- SVi + 1
     if vs = 1 then
         if RA = 0 then
-            VL <- (RA)
+            VL <- (RA)[57:63]
         else
-            VL <- VLimm
+            VL <- VLimm[2:8]
     else
         VL <- SVSTATE[7:13]
     if ms = 1 then
-        MVL <- VLimm
+        MVL <- VLimm[2:8]
     else
         MVL <- SVSTATE[0:6]
     if VL > MVL then
@@ -24,7 +24,7 @@ Pseudo-code:
     SVSTATE[0:6] = MVL
     SVSTATE[7:13] = VL
     if RT != 0 then
-        RT <- VL
+        RT <- VL || [0] * 58
 
 Special Registers Altered: